26 lines
399 B
Plaintext
26 lines
399 B
Plaintext
//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Thu Apr 11 06:15:18 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/lab2.v"
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//file1 "\C:/cygwin64/home/koray/verilog/lab2/src/tb.v"
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`timescale 100 ps/100 ps
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module tb (
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)
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;
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wire VCC;
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wire GND;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* tb */
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