verilog/gowin/fpga_project/impl/pnr/fpga_project.tr.html
2024-07-05 19:15:16 +03:00

11 lines
349 B
HTML

<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
</head>
<frameset cols="20%, 80%">
<frame src="fpga_project_tr_cata.html" name="cataFrame" />
<frame src="fpga_project_tr_content.html" name="mainFrame"/>
</frameset>
</html>