88 lines
2.4 KiB
JSON
88 lines
2.4 KiB
JSON
{
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"BACKGROUND_PROGRAMMING" : "off",
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"COMPRESS" : false,
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"CPU" : false,
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"CRC_CHECK" : true,
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"Clock_Route_Order" : 0,
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"Correct_Hold_Violation" : true,
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"DONE" : false,
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"DOWNLOAD_SPEED" : "default",
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"Disable_Insert_Pad" : false,
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"ENABLE_CTP" : false,
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"ENABLE_MERGE_MODE" : false,
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"ENCRYPTION_KEY" : false,
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"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
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"ERROR_DECTION_AND_CORRECTION" : false,
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"ERROR_DECTION_ONLY" : false,
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"ERROR_INJECTION" : false,
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"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
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"Enable_DSRM" : false,
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"FORMAT" : "binary",
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"FREQUENCY_DIVIDER" : "",
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"Generate_Constraint_File_of_Ports" : false,
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"Generate_IBIS_File" : false,
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"Generate_Plain_Text_Timing_Report" : false,
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"Generate_Post_PNR_Simulation_Model_File" : false,
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"Generate_Post_Place_File" : false,
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"Generate_SDF_File" : false,
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"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
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"Global_Freq" : "default",
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"GwSyn_Loop_Limit" : 2000,
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"HOTBOOT" : false,
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"I2C" : false,
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"I2C_SLAVE_ADDR" : "00",
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"IncludePath" : [
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],
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"Incremental_Compile" : "",
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"Initialize_Primitives" : false,
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"JTAG" : false,
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"MODE_IO" : false,
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"MSPI" : false,
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"MSPI_JUMP" : false,
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"MULTIBOOT_ADDRESS_WIDTH" : "24",
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"MULTIBOOT_MODE" : "Normal",
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"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
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"MULTIJUMP_ADDRESS_WIDTH" : "24",
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"MULTIJUMP_MODE" : "Normal",
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"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
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"Multi_Boot" : true,
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"OUTPUT_BASE_NAME" : "fpga_project",
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"POWER_ON_RESET_MONITOR" : true,
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"PRINT_BSRAM_VALUE" : true,
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"PROGRAM_DONE_BYPASS" : false,
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"PlaceInRegToIob" : true,
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"PlaceIoRegToIob" : true,
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"PlaceOutRegToIob" : true,
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"Place_Option" : "0",
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"Process_Configuration_Verion" : "1.0",
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"Promote_Physical_Constraint_Warning_to_Error" : true,
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"READY" : false,
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"RECONFIG_N" : false,
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"Ram_RW_Check" : false,
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"Replicate_Resources" : false,
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"Report_Auto-Placed_Io_Information" : false,
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"Route_Maxfan" : 23,
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"Route_Option" : "0",
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"Run_Timing_Driven" : true,
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"SECURE_MODE" : false,
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"SECURITY_BIT" : true,
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"SEU_HANDLER" : false,
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"SEU_HANDLER_CHECKSUM" : false,
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"SEU_HANDLER_MODE" : "auto",
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"SSPI" : false,
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"STOP_SEU_HANDLER" : false,
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"Show_All_Warnings" : false,
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"Synthesize_tool" : "GowinSyn",
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"TclPre" : "",
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"TopModule" : "",
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"USERCODE" : "default",
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"Unused_Pin" : "As_input_tri_stated_with_pull_up",
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"VCCAUX" : 3.3,
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"VCCX" : "3.3",
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"VHDL_Standard" : "VHDL_Std_1993",
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"Verilog_Standard" : "Vlg_Std_2001",
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"WAKE_UP" : "0",
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"show_all_warnings" : false,
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"turn_off_bg" : false
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} |