15 lines
597 B
XML
15 lines
597 B
XML
<?xml version="1" encoding="UTF-8"?>
|
|
<!DOCTYPE gowin-fpga-project>
|
|
<Project>
|
|
<Template>FPGA</Template>
|
|
<Version>5</Version>
|
|
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
|
<FileList>
|
|
<File path="src/bit3adder.v" type="file.verilog" enable="1"/>
|
|
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
|
|
<File path="src/halfadder.v" type="file.verilog" enable="1"/>
|
|
<File path="src/ledTest.v" type="file.verilog" enable="1"/>
|
|
<File path="src/fpga_project.cst" type="file.cst" enable="1"/>
|
|
</FileList>
|
|
</Project>
|