99 lines
817 B
Plaintext
99 lines
817 B
Plaintext
$date
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Sun Jul 7 02:46:47 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module seqBlinkTB $end
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$var wire 4 ! leds [3:0] $end
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$var reg 1 " clock $end
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$scope module uut $end
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$var wire 1 " clock $end
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$var reg 2 # count [1:0] $end
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$var reg 4 $ leds [3:0] $end
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$var reg 4 % start [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b1 %
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bx $
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b0 #
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0"
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bx !
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$end
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#5
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b1 !
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b1 $
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b1 #
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1"
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#10
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0"
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#15
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b10 !
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b10 $
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b10 #
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1"
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#20
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0"
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#25
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b100 !
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b100 $
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b11 #
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1"
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#30
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0"
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#35
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b1000 !
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b1000 $
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b0 #
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1"
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#40
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0"
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#45
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b1 !
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b1 $
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b1 #
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1"
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#50
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0"
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#55
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b10 !
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b10 $
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b10 #
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1"
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#60
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0"
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#65
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b100 !
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b100 $
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b11 #
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1"
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#70
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0"
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#75
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b1000 !
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b1000 $
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b0 #
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1"
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#80
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0"
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#85
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b1 !
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b1 $
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b1 #
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1"
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#90
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0"
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#95
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b10 !
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b10 $
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b10 #
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1"
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#100
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0"
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