28 lines
582 B
Verilog
28 lines
582 B
Verilog
module timer (
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input clock,
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input reset,
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input gate,
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input [2:0] counter,
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input way,
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output reg [5:0] count
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);
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reg [5:0] countReg;
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always@(posedge clock or posedge reset) begin
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if (reset) begin
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countReg <= 6'd0;
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end
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else if (gate) begin
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if (way && (countReg != 6'b111_111)) begin
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countReg <= countReg + counter;
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end
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else if (!way && (countReg != 6'b000_000)) begin
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countReg <= countReg - counter;
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end
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end
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end
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assign count = countReg;
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endmodule |