42 lines
517 B
Plaintext
42 lines
517 B
Plaintext
$date
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Fri Jul 5 05:10:51 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module lab4tb $end
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$var wire 4 ! s2 [3:0] $end
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$var reg 9 " s1 [8:0] $end
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$scope module uut $end
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$var wire 9 # signal [8:0] $end
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$var reg 4 $ S [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b110 $
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b100101001 #
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b100101001 "
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b110 !
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$end
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#10
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b100 !
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b100 $
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b10101001 "
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b10101001 #
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#20
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b1 !
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b1 $
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b1101001 "
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b1101001 #
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#30
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b101 !
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b101 $
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b101001 "
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b101001 #
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#40
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