22 lines
492 B
Verilog
22 lines
492 B
Verilog
module lab4(
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input [8:0] signal,
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output reg [3:0] S
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);
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always@(*) begin
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S = 4'b0000;
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if (signal[8] == 1) begin //First most significant bit -> sum
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S = signal[5:3] + signal[2:0];
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end
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else if (signal[7] == 1) begin
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S = signal[5:3] - signal [2:0];
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end
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else if (signal[6] == 1) begin
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S = signal[5:3] & signal [2:0];
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end
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else if (signal[6] == 0) begin
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S = signal[5:3] | signal [2:0];
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end
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end
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endmodule |