19 lines
309 B
Verilog
19 lines
309 B
Verilog
module halfaddertb ();
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reg A, B;
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wire S, C;
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halfadder uut(
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.A(A), .B(B), .S(S), .C(C)
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);
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initial begin
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$dumpfile("hadmp.vcd");
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$dumpvars;
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A = 1'b0; B = 1'b0; #10;
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A = 1'b0; B = 1'b1; #10;
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A = 1'b1; B = 1'b0; #10;
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A = 1'b1; B = 1'b1; #10;
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end
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endmodule
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