22 lines
304 B
Verilog
22 lines
304 B
Verilog
module lab4tb();
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reg [8:0] s1;
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wire [3:0] s2;
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lab4 uut(
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.signal(s1),
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.S(s2)
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);
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initial begin
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$dumpfile("lab4v.vcd");
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$dumpvars;
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s1 = 9'b100_101_001; #10;
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s1 = 9'b010_101_001; #10;
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s1 = 9'b001_101_001; #10;
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s1 = 9'b000_101_001; #10;
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$display("Done");
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end
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endmodule |