42 lines
1.0 KiB
Verilog
42 lines
1.0 KiB
Verilog
module subtractionTB;
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reg [3:0] A, B;
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reg BorrowIN;
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wire [3:0] Y;
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wire BorrowOUT;
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// Instantiate the subtraction module
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subtraction uut (
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.A(A),
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.B(B),
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.BorrowIN(BorrowIN),
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.Y(Y),
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.BorrowOUT(BorrowOUT)
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);
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initial begin
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$dumpfile("subtraction.vcd");
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$dumpvars;
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// Initialize inputs
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A = 4'b0000; // Set A to 0
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B = 4'b0000; // Set B to 0
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BorrowIN = 0; // No borrow input
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// Apply test cases
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#10 A = 4'b0110; B = 4'b0010; BorrowIN = 0; // A = 6, B = 2
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#10 A = 4'b0010; B = 4'b0110; BorrowIN = 0; // A = 2, B = 6
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#10 A = 4'b1100; B = 4'b0100; BorrowIN = 0; // A = -4, B = 4
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#10 A = 4'b1000; B = 4'b1000; BorrowIN = 0; // A = -8, B = -8
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#10 A = 4'b1111; B = 4'b0001; BorrowIN = 1; // A = -1, B = 1, with borrow input
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// Wait for the results
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#10 $finish;
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end
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initial begin
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// Monitor the values of Y and overflow
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$monitor("At time %t: A = %b, B = %b, Y = %b, BorrowOut = %b, overflow = %b", $time, A, B, Y, BorrowOut, overflow);
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end
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endmodule
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