26 lines
603 B
Verilog
26 lines
603 B
Verilog
module opCode (
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input [2:0] A,
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output [7:0] opCode
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);
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wire and1, and2, and3, and4, notA, notB, notC;
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not n1(notA, A[2]);
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not n2(notB, A[1]);
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not n3(notC, A[0]);
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and a01(and1, A[2], A[1]);
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and a02(and2, notA, A[1]);
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and a03(and3, A[2], notB);
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and a04(and4, notA, notB);
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and a1(opCode[0], and4, notC);
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and a2(opCode[1], and4, A[0]);
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and a3(opCode[2], and2, notC);
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and a4(opCode[3], and2, A[0]);
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and a5(opCode[4], and3, notC);
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and a6(opCode[5], and3, A[0]);
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and a7(opCode[6], and1, notC);
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and a8(opCode[7], and1, A[0]);
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endmodule
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