29 lines
793 B
Verilog
29 lines
793 B
Verilog
module arithmeticUnit (
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input [1:0] opCode,
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input [3:0] A, B,
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input CarryIN,
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output [3:0] add_Y, sub_Y,
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output CarryOUT,
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output overflow
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);
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wire [3:0] addY, subY;
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wire CarryOUTADD, CarryOUTSUB;
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addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(overflow));
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subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
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and add1 (add_Y[0], opCode[0], addY[0]);
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and add2 (add_Y[1], opCode[0], addY[1]);
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and add3 (add_Y[2], opCode[0], addY[2]);
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and add4 (add_Y[3], opCode[0], addY[3]);
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and sub1 (sub_Y[0], opCode[1], subY[0]);
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and sub2 (sub_Y[1], opCode[1], subY[1]);
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and sub3 (sub_Y[2], opCode[1], subY[2]);
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and sub4 (sub_Y[3], opCode[1], subY[3]);
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or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB);
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endmodule
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