21 lines
665 B
Verilog
21 lines
665 B
Verilog
module addition (
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input [3:0] A, B,
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input CarryIN,
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output [3:0] Y,
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output CarryOUT,
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output overflow
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);
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wire [2:0] Carry4;
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fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
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fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
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fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
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fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
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//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
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xor ov1 (overflow, Carry4[2], CarryOUT);
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endmodule
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