42 lines
820 B
Verilog
42 lines
820 B
Verilog
module tetris(
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input clk,
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input [2:0] parca,
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output reg [4:0] yukseklik,
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output [4:0] cevrim,
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output bitti_mi
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);
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reg [4:0] cevrim_r = 0;
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reg [4:0] y_0 = 0;
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reg [4:0] y_1 = 0;
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reg [4:0] y_2 = 0;
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assign cevrim = cevrim_r;
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assign bitti_mi = cevrim_r == 5'b10000;
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always @(posedge clk) begin
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if (cevrim != 5'b10000) begin
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cevrim_r <= cevrim_r + 5'd1;
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y_0 <= y_0 + {4'b0000, parca[0]};
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y_1 <= y_1 + {4'b0000, parca[1]};
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y_2 <= y_2 + {4'b0000, parca[2]};
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end
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end
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/* always @(posedge bitti_mi)
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yukseklik <= y_0 > y_1
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? y_0 > y_2 ? y_0 : y_2
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: y_1 > y_2 ? y_1 : y_2;
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*/
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always @(posedge bitti_mi) begin
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if (y_0 > y_1) begin
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if (y_0 > y_2) yukseklik <= y_0;
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else yukseklik <= y_2;
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end else if (y_0 > y_1) begin
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if (y_1 > y_2) yukseklik <= y_1;
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else yukseklik <= y_2;
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end
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end
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endmodule
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