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verilog/gowin/fpga_project/src
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k0rrluna c1f0851a45 verilog
2024-07-05 19:15:16 +03:00
..
bit3adder.v
verilog
2024-07-05 19:15:16 +03:00
fpga_project.cst
verilog
2024-07-05 19:15:16 +03:00
fulladder.v
verilog
2024-07-05 19:15:16 +03:00
halfadder.v
verilog
2024-07-05 19:15:16 +03:00
ledTest.v
verilog
2024-07-05 19:15:16 +03:00