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verilog/iverilog/tobb/labs/lab3/src/fullAdder.v
2024-12-01 02:01:08 +03:00

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Coq

module fullAdder(
input A, B, Z,
output S, C
);
wire W0, W1, W2;
halfAdder h0(A, B, W0, W1);
halfAdder h1(W0, Z, S, W2);
or(C, W1, W2);
endmodule