24 lines
330 B
Verilog
24 lines
330 B
Verilog
module tb();
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reg r1, r2;
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wire w1, w2;
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halfAdder uut(
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.A(r1),
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.B(r2),
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.S(w1),
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.C(w2)
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);
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initial begin
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$dumpfile("dmp.vcd");
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$dumpvars;
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r1 = 0; r2 = 0; #20
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r1 = 1; r2 = 0; #20
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r1 = 0; r2 = 1; #20
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r1 = 1; r2 = 1; #20
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$display(w1);
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$display(w2);
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end
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endmodule |