1657 lines
16 KiB
Plaintext
1657 lines
16 KiB
Plaintext
$date
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Sun Dec 15 04:15:16 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module ALUTB $end
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$var wire 1 ! overflow $end
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$var wire 4 " Y [3:0] $end
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$var wire 1 # CarryOUT $end
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$var reg 4 $ A [3:0] $end
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$var reg 4 % B [3:0] $end
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$var reg 1 & CarryIN $end
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$var reg 3 ' opCodeA [2:0] $end
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$scope module uut $end
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$var wire 4 ( A [3:0] $end
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$var wire 4 ) B [3:0] $end
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$var wire 1 & CarryIN $end
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$var wire 3 * opCodeA [2:0] $end
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$var wire 4 + wireY [3:0] $end
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$var wire 4 , sub_Y [3:0] $end
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$var wire 4 - resultX [3:0] $end
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$var wire 4 . resultO [3:0] $end
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$var wire 4 / resultA [3:0] $end
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$var wire 1 ! overflow $end
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$var wire 8 0 opCode8 [7:0] $end
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$var wire 4 1 lUOutput2 [3:0] $end
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$var wire 4 2 lUOutput1 [3:0] $end
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$var wire 4 3 add_Y [3:0] $end
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$var wire 4 4 aUtemp2 [3:0] $end
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$var wire 4 5 aUtemp1 [3:0] $end
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$var wire 4 6 Y [3:0] $end
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$var wire 1 # CarryOUT $end
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$scope module aU $end
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$var wire 4 7 A [3:0] $end
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$var wire 4 8 B [3:0] $end
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$var wire 1 & CarryIN $end
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$var wire 1 # CarryOUT $end
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$var wire 2 9 opCode [1:0] $end
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$var wire 1 ! overflow $end
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$var wire 4 : sub_Y [3:0] $end
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$var wire 4 ; subY [3:0] $end
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$var wire 1 < overflowSUB $end
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$var wire 1 = overflowADD $end
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$var wire 4 > add_Y [3:0] $end
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$var wire 4 ? addY [3:0] $end
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$var wire 1 @ CarryOUTSUB $end
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$var wire 1 A CarryOUTADD $end
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$scope module a1 $end
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$var wire 4 B A [3:0] $end
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$var wire 4 C B [3:0] $end
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$var wire 1 & CarryIN $end
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$var wire 1 = overflow $end
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$var wire 4 D Y [3:0] $end
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$var wire 1 A CarryOUT $end
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$var wire 4 E Carry4 [3:0] $end
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$scope module f0 $end
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$var wire 1 F A $end
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$var wire 1 G B $end
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$var wire 1 & Carry $end
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$var wire 1 H CarryO $end
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$var wire 1 I xor1 $end
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$var wire 1 J and2 $end
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$var wire 1 K and1 $end
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$var wire 1 L Sum $end
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$scope module h1 $end
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$var wire 1 F A $end
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$var wire 1 G B $end
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$var wire 1 K Carry $end
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$var wire 1 I Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 I A $end
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$var wire 1 & B $end
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$var wire 1 J Carry $end
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$var wire 1 L Sum $end
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$upscope $end
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$upscope $end
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$scope module f1 $end
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$var wire 1 M A $end
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$var wire 1 N B $end
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$var wire 1 O Carry $end
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$var wire 1 P CarryO $end
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$var wire 1 Q xor1 $end
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$var wire 1 R and2 $end
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$var wire 1 S and1 $end
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$var wire 1 T Sum $end
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$scope module h1 $end
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$var wire 1 M A $end
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$var wire 1 N B $end
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$var wire 1 S Carry $end
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$var wire 1 Q Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 Q A $end
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$var wire 1 O B $end
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$var wire 1 R Carry $end
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$var wire 1 T Sum $end
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$upscope $end
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$upscope $end
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$scope module f2 $end
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$var wire 1 U A $end
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$var wire 1 V B $end
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$var wire 1 W Carry $end
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$var wire 1 X CarryO $end
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$var wire 1 Y xor1 $end
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$var wire 1 Z and2 $end
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$var wire 1 [ and1 $end
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$var wire 1 \ Sum $end
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$scope module h1 $end
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$var wire 1 U A $end
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$var wire 1 V B $end
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$var wire 1 [ Carry $end
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$var wire 1 Y Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 Y A $end
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$var wire 1 W B $end
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$var wire 1 Z Carry $end
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$var wire 1 \ Sum $end
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$upscope $end
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$upscope $end
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$scope module f3 $end
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$var wire 1 ] A $end
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$var wire 1 ^ B $end
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$var wire 1 _ Carry $end
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$var wire 1 A CarryO $end
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$var wire 1 ` xor1 $end
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$var wire 1 a and2 $end
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$var wire 1 b and1 $end
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$var wire 1 c Sum $end
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$scope module h1 $end
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$var wire 1 ] A $end
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$var wire 1 ^ B $end
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$var wire 1 b Carry $end
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$var wire 1 ` Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 ` A $end
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$var wire 1 _ B $end
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$var wire 1 a Carry $end
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$var wire 1 c Sum $end
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$upscope $end
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$upscope $end
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$scope module od1 $end
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$var wire 4 d A [3:0] $end
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$var wire 4 e B [3:0] $end
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$var wire 1 A CarryOUT $end
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$var wire 4 f Y [3:0] $end
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$var wire 1 g addOverflow $end
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$var wire 1 h detect1 $end
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$var wire 1 i detect2 $end
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$var wire 1 j opC $end
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$var wire 2 k opCode [1:0] $end
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$var wire 1 = overflowDetect $end
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$var wire 1 l sign1 $end
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$var wire 1 m sign2 $end
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$var wire 1 n sign3 $end
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$var wire 1 o subOverflow $end
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$upscope $end
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$upscope $end
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$scope module s1 $end
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$var wire 4 p A [3:0] $end
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$var wire 4 q B [3:0] $end
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$var wire 1 & CarryIN $end
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$var wire 4 r xB [3:0] $end
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$var wire 1 < overflow $end
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$var wire 4 s notB [3:0] $end
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$var wire 4 t Y1 [3:0] $end
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$var wire 4 u Y [3:0] $end
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$var wire 1 @ CarryOUT $end
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$scope module a1 $end
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$var wire 4 v A [3:0] $end
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$var wire 4 w B [3:0] $end
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$var wire 1 x CarryIN $end
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$var wire 1 y overflow $end
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$var wire 4 z Y [3:0] $end
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$var wire 1 { CarryOUT $end
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$var wire 4 | Carry4 [3:0] $end
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$scope module f0 $end
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$var wire 1 } A $end
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$var wire 1 ~ B $end
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$var wire 1 x Carry $end
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$var wire 1 !" CarryO $end
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$var wire 1 "" xor1 $end
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$var wire 1 #" and2 $end
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$var wire 1 $" and1 $end
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$var wire 1 %" Sum $end
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$scope module h1 $end
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$var wire 1 } A $end
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$var wire 1 ~ B $end
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$var wire 1 $" Carry $end
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$var wire 1 "" Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 "" A $end
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$var wire 1 x B $end
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$var wire 1 #" Carry $end
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$var wire 1 %" Sum $end
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$upscope $end
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$upscope $end
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$scope module f1 $end
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$var wire 1 &" A $end
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$var wire 1 '" B $end
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$var wire 1 (" Carry $end
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$var wire 1 )" CarryO $end
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$var wire 1 *" xor1 $end
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$var wire 1 +" and2 $end
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$var wire 1 ," and1 $end
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$var wire 1 -" Sum $end
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$scope module h1 $end
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$var wire 1 &" A $end
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$var wire 1 '" B $end
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$var wire 1 ," Carry $end
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$var wire 1 *" Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 *" A $end
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$var wire 1 (" B $end
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$var wire 1 +" Carry $end
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$var wire 1 -" Sum $end
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$upscope $end
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$upscope $end
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$scope module f2 $end
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$var wire 1 ." A $end
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$var wire 1 /" B $end
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$var wire 1 0" Carry $end
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$var wire 1 1" CarryO $end
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$var wire 1 2" xor1 $end
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$var wire 1 3" and2 $end
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$var wire 1 4" and1 $end
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$var wire 1 5" Sum $end
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$scope module h1 $end
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$var wire 1 ." A $end
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$var wire 1 /" B $end
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$var wire 1 4" Carry $end
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$var wire 1 2" Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 2" A $end
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$var wire 1 0" B $end
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$var wire 1 3" Carry $end
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$var wire 1 5" Sum $end
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$upscope $end
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$upscope $end
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$scope module f3 $end
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$var wire 1 6" A $end
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$var wire 1 7" B $end
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$var wire 1 8" Carry $end
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$var wire 1 { CarryO $end
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$var wire 1 9" xor1 $end
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$var wire 1 :" and2 $end
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$var wire 1 ;" and1 $end
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$var wire 1 <" Sum $end
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$scope module h1 $end
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$var wire 1 6" A $end
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$var wire 1 7" B $end
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$var wire 1 ;" Carry $end
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$var wire 1 9" Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 9" A $end
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$var wire 1 8" B $end
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$var wire 1 :" Carry $end
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$var wire 1 <" Sum $end
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$upscope $end
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$upscope $end
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$scope module od1 $end
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$var wire 4 =" A [3:0] $end
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$var wire 4 >" B [3:0] $end
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$var wire 1 { CarryOUT $end
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$var wire 4 ?" Y [3:0] $end
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$var wire 1 @" addOverflow $end
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$var wire 1 A" detect1 $end
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$var wire 1 B" detect2 $end
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$var wire 1 C" opC $end
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$var wire 2 D" opCode [1:0] $end
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$var wire 1 y overflowDetect $end
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$var wire 1 E" sign1 $end
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$var wire 1 F" sign2 $end
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$var wire 1 G" sign3 $end
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$var wire 1 H" subOverflow $end
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$upscope $end
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$upscope $end
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$scope module a2 $end
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$var wire 4 I" A [3:0] $end
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$var wire 4 J" B [3:0] $end
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$var wire 1 & CarryIN $end
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$var wire 1 K" overflow $end
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$var wire 4 L" Y [3:0] $end
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$var wire 1 @ CarryOUT $end
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$var wire 4 M" Carry4 [3:0] $end
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$scope module f0 $end
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$var wire 1 N" A $end
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$var wire 1 O" B $end
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$var wire 1 & Carry $end
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$var wire 1 P" CarryO $end
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$var wire 1 Q" xor1 $end
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$var wire 1 R" and2 $end
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$var wire 1 S" and1 $end
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$var wire 1 T" Sum $end
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$scope module h1 $end
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$var wire 1 N" A $end
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$var wire 1 O" B $end
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$var wire 1 S" Carry $end
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$var wire 1 Q" Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 Q" A $end
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$var wire 1 & B $end
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$var wire 1 R" Carry $end
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$var wire 1 T" Sum $end
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$upscope $end
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$upscope $end
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$scope module f1 $end
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$var wire 1 U" A $end
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$var wire 1 V" B $end
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$var wire 1 W" Carry $end
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$var wire 1 X" CarryO $end
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$var wire 1 Y" xor1 $end
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$var wire 1 Z" and2 $end
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$var wire 1 [" and1 $end
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$var wire 1 \" Sum $end
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$scope module h1 $end
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$var wire 1 U" A $end
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$var wire 1 V" B $end
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$var wire 1 [" Carry $end
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$var wire 1 Y" Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 Y" A $end
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$var wire 1 W" B $end
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$var wire 1 Z" Carry $end
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$var wire 1 \" Sum $end
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$upscope $end
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$upscope $end
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$scope module f2 $end
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$var wire 1 ]" A $end
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$var wire 1 ^" B $end
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$var wire 1 _" Carry $end
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$var wire 1 `" CarryO $end
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$var wire 1 a" xor1 $end
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$var wire 1 b" and2 $end
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$var wire 1 c" and1 $end
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$var wire 1 d" Sum $end
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$scope module h1 $end
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$var wire 1 ]" A $end
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$var wire 1 ^" B $end
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$var wire 1 c" Carry $end
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$var wire 1 a" Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 a" A $end
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$var wire 1 _" B $end
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$var wire 1 b" Carry $end
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$var wire 1 d" Sum $end
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$upscope $end
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$upscope $end
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$scope module f3 $end
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$var wire 1 e" A $end
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$var wire 1 f" B $end
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$var wire 1 g" Carry $end
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$var wire 1 @ CarryO $end
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$var wire 1 h" xor1 $end
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$var wire 1 i" and2 $end
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$var wire 1 j" and1 $end
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$var wire 1 k" Sum $end
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$scope module h1 $end
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$var wire 1 e" A $end
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$var wire 1 f" B $end
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$var wire 1 j" Carry $end
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$var wire 1 h" Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 h" A $end
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$var wire 1 g" B $end
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$var wire 1 i" Carry $end
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$var wire 1 k" Sum $end
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$upscope $end
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$upscope $end
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$scope module od1 $end
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$var wire 4 l" A [3:0] $end
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$var wire 4 m" B [3:0] $end
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$var wire 1 @ CarryOUT $end
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$var wire 4 n" Y [3:0] $end
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$var wire 1 o" addOverflow $end
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$var wire 1 p" detect1 $end
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$var wire 1 q" detect2 $end
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$var wire 1 r" opC $end
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$var wire 2 s" opCode [1:0] $end
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$var wire 1 K" overflowDetect $end
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$var wire 1 t" sign1 $end
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$var wire 1 u" sign2 $end
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$var wire 1 v" sign3 $end
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$var wire 1 w" subOverflow $end
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$upscope $end
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$upscope $end
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$scope module od1 $end
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$var wire 4 x" A [3:0] $end
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$var wire 4 y" B [3:0] $end
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$var wire 1 @ CarryOUT $end
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$var wire 4 z" Y [3:0] $end
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$var wire 1 {" addOverflow $end
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$var wire 1 |" detect1 $end
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$var wire 1 }" detect2 $end
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$var wire 1 ~" opC $end
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$var wire 2 !# opCode [1:0] $end
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$var wire 1 < overflowDetect $end
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$var wire 1 "# sign1 $end
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$var wire 1 ## sign2 $end
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$var wire 1 $# sign3 $end
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$var wire 1 %# subOverflow $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module lU $end
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$var wire 4 &# A [3:0] $end
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$var wire 4 '# B [3:0] $end
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$var wire 3 (# opCode [2:0] $end
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$var wire 4 )# xor1 [3:0] $end
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$var wire 4 *# resultX [3:0] $end
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$var wire 4 +# resultO [3:0] $end
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$var wire 4 ,# resultA [3:0] $end
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$var wire 4 -# or1 [3:0] $end
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$var wire 4 .# and1 [3:0] $end
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$upscope $end
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$scope module opCd $end
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$var wire 3 /# A [2:0] $end
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$var wire 1 0# and1 $end
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$var wire 1 1# and2 $end
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$var wire 1 2# and3 $end
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$var wire 1 3# and4 $end
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$var wire 1 4# notA $end
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$var wire 1 5# notB $end
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$var wire 1 6# notC $end
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$var wire 8 7# opCode [7:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b1 7#
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16#
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15#
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14#
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13#
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02#
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01#
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00#
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b0 /#
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b0 .#
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b0 -#
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b0 ,#
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b0 +#
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b0 *#
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b0 )#
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b0 (#
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b0 '#
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b0 &#
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0%#
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0$#
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0##
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1"#
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b10 !#
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1~"
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0}"
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0|"
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0{"
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b0 z"
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b0 y"
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b0 x"
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0w"
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0v"
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0u"
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1t"
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b1 s"
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1r"
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0q"
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|
1p"
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|
1o"
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b0 n"
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b0 m"
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b0 l"
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0k"
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0j"
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0i"
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0h"
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0g"
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0f"
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