32 lines
464 B
Verilog
32 lines
464 B
Verilog
module tetrisTB();
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reg [2:0] p;
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reg clk;
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wire [3:0] yukseklik;
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wire bitti_mi;
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wire [3:0] cevrim;
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tetris uut (
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.parca(p),
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.clk(clk),
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.yukseklik(yukseklik),
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.bitti_mi(bitti_mi),
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.cevrim(cevrim)
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);
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always begin
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clk = ~clk; #1;
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end
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initial begin
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$dumpfile("tetris.vcd");
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$dumpvars;
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clk = 0; p = 3'b010; #2;
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p = 3'b011; #2;
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p = 3'b010; #2;
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p = 3'b000; #30;
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$finish;
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end
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endmodule
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