23 lines
252 B
Verilog
23 lines
252 B
Verilog
module knightRiderTB();
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reg clk;
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wire [7:0] leds;
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knightRider uut (
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.clk(clk),
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.leds(leds)
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);
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always begin
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clk = ~clk; #2;
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end
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initial begin
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$dumpfile("knightRider.vcd");
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$dumpvars;
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clk = 0; #50;
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$finish;
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end
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endmodule
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