105 lines
783 B
Plaintext
105 lines
783 B
Plaintext
$date
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Sat Jan 25 05:37:22 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module knightRiderTB $end
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$var wire 8 ! leds [7:0] $end
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$var reg 1 " clk $end
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$scope module uut $end
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$var wire 1 " clk $end
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$var reg 1 # direction $end
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$var reg 8 $ leds [7:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b111 $
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0#
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0"
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b111 !
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$end
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#2
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b1110 !
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b1110 $
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1"
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#4
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0"
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#6
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b11100 !
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b11100 $
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1"
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#8
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0"
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#10
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b111000 !
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b111000 $
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1"
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#12
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0"
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#14
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b1110000 !
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b1110000 $
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1"
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#16
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0"
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#18
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b11100000 !
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b11100000 $
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1"
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#20
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0"
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#22
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b1110000 !
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b1110000 $
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1#
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1"
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#24
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0"
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#26
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b111000 !
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b111000 $
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1"
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#28
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0"
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#30
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b11100 !
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b11100 $
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1"
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#32
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0"
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#34
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b1110 !
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b1110 $
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1"
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#36
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0"
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#38
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b111 !
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b111 $
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1"
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#40
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0"
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#42
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b1110 !
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b1110 $
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0#
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1"
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#44
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0"
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#46
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b11100 !
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b11100 $
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1"
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#48
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0"
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#50
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b111000 !
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b111000 $
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1"
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