verilog/iverilog/tobb/lab5/knightRider.v
2025-01-25 08:00:40 +03:00

32 lines
564 B
Verilog

module knightRider (
input clk,
output reg [7:0] leds
);
reg direction;
initial begin
leds = 8'b0000_0111;
direction = 1'b0; // 0 left to right
end
always@(posedge clk) begin
if (direction == 0) begin
if (leds == 8'b1110_0000) begin
direction <= 1;
leds <= leds >> 1;
end else begin
leds <= leds << 1;
end
end else begin
if (leds == 8'b0000_0111) begin
direction <= 0;
leds <= leds << 1;
end else begin
leds <= leds >> 1;
end
end
end
endmodule