44 lines
1.1 KiB
Verilog
44 lines
1.1 KiB
Verilog
module ayarliSayac (
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input clk, rst, en,
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input [2:0] sayma_miktari,
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input sayma_yonu,
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output reg [5:0] sayac
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);
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reg [2:0] miktar;
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reg [1:0] clk_divider;
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initial begin
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sayac = 6'b0000_00;
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miktar = 3'b001;
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clk_divider = 2'b00;
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end
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always @(negedge clk or posedge rst) begin
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if (rst) begin
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sayac <= 6'b0000_00;
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clk_divider <= 2'b00;
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end else begin
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clk_divider <= clk_divider + 1;
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end
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if (clk_divider == 2'b11) begin
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if (en) begin
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miktar = sayma_miktari;
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if (sayma_yonu == 1) begin
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if (sayac + miktar >= 6'b1111_11) begin
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sayac <= 6'b1111_11;
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end else begin
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sayac <= miktar + sayac;
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end
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end else begin
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if (sayac - miktar <= 6'b0000_00) begin
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sayac <= 6'b0000_00;
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end else begin
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sayac <= sayac - miktar;
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end
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end
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end
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end
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end
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endmodule
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