23 lines
283 B
Verilog
23 lines
283 B
Verilog
module sube3soru2TB();
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reg [9:0] A;
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reg [5:0] B;
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wire [4:0] D,l1,l2;
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sube3soru2 uut (
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.A(A),
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.B(B),
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.D(D),
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.l1(l1),
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.l2(l2)
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);
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initial begin
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$dumpfile("sube3soru2.vcd");
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$dumpvars;
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A = 10'b0000011001; B = 6'b000011; #5;
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$finish;
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end
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endmodule
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