45 lines
698 B
Plaintext
45 lines
698 B
Plaintext
$date
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Sat Jan 25 03:14:14 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module sube3soru2TB $end
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$var wire 5 ! l2 [4:0] $end
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$var wire 5 " l1 [4:0] $end
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$var wire 5 # D [4:0] $end
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$var reg 10 $ A [9:0] $end
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$var reg 6 % B [5:0] $end
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$scope module uut $end
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$var wire 10 & A [9:0] $end
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$var wire 6 ' B [5:0] $end
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$var reg 5 ( D [4:0] $end
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$var reg 5 ) l1 [4:0] $end
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$var reg 5 * l2 [4:0] $end
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$var integer 32 + hunderedR [31:0] $end
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$var integer 32 , tempD [31:0] $end
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$var integer 32 - tempO [31:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b11010000 -
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b11001 ,
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b1001011000 +
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b1000 *
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b0 )
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b10 (
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b11 '
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b11001 &
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b11 %
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b11001 $
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b10 #
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b0 "
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b1000 !
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$end
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#5
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