25 lines
434 B
Verilog
25 lines
434 B
Verilog
module sube3soru2 (
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input [9:0] A,
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input [5:0] B,
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output reg [4:0] D,l1,l2
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);
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integer tempD, tempO, hunderedR;
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always@(A or B) begin
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hunderedR = A[9:2] * 100;
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case(A[1:0])
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2'b01: tempD = 25;
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2'b10: tempD = 50;
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2'b11: tempD = 75;
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default: tempD = 00;
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endcase
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tempO = hunderedR + tempD;
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tempO = tempO / B;
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D = tempO / 100;
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l1 = (tempO%100)/10;
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l2 = tempO%10;
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end
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endmodule
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