26 lines
414 B
Verilog
26 lines
414 B
Verilog
module bib3TB();
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reg [8:0] A;
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wire [3:0] Y;
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bib3 uut (
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.buyruk(A),
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.sonuc(Y)
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);
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initial begin
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$dumpfile("bib3.vcd");
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$dumpvars;
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A = 9'b000_001_001; #5;
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A = 9'b001_100_001; #5;
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A = 9'b010_100_101; #5;
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A = 9'b011_100_011; #5;
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A = 9'b100_111_111; #5;
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A = 9'b100_100_001; #5;
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A = 9'b101_100_001; #5;
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A = 9'b110_100_001; #5;
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A = 9'b111_100_001; #5;
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end
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endmodule
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