Synthesis Messages

Report Title	GowinSynthesis Report
Design File	\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.9.03 Education (64-bit)
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Device Version	C
Created Time	Mon Jan 20 18:30:58 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	bttn
Synthesis Process	Running parser:     CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.315s, Peak memory usage = 175.059MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 175.059MB     Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 175.059MB     Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 175.059MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 175.059MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 175.059MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 175.059MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 175.059MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 175.070MB     Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 206.203MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 206.203MB Generate output files:     CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 206.203MB
Total Time and Memory Usage	CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 206.203MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	28
I/O Buf	28
IBUF	14
OBUF	14
LUT	141
LUT2	16
LUT3	36
LUT4	89

Resource Utilization Summary

Resource	Usage	Utilization
Logic	141(141 LUT, 0 ALU) / 20736	<1%
Register	0 / 16173	0%
--Register as Latch	0 / 16173	0%
--Register as FF	0 / 16173	0%
BSRAM	0 / 46	0%