$date
	Sat Dec 14 04:55:25 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module subtractionTB $end
$var wire 1 ! overflow $end
$var wire 5 " Y [4:0] $end
$var reg 4 # A [3:0] $end
$var reg 4 $ B [3:0] $end
$scope module uut $end
$var wire 4 % A [3:0] $end
$var wire 4 & B [3:0] $end
$var wire 4 ' xB [3:0] $end
$var wire 1 ( overflow $end
$var wire 5 ) notB [4:0] $end
$var wire 5 * Y1 [4:0] $end
$var wire 5 + Y [4:0] $end
$scope module a1 $end
$var wire 4 , A [3:0] $end
$var wire 4 - B [3:0] $end
$var wire 5 . Y [4:0] $end
$var wire 4 / Carry4 [3:0] $end
$scope module f1 $end
$var wire 1 0 A $end
$var wire 1 1 B $end
$var wire 1 2 Carry $end
$var wire 1 3 CarryO $end
$var wire 1 4 xor1 $end
$var wire 1 5 and2 $end
$var wire 1 6 and1 $end
$var wire 1 7 Sum $end
$scope module h1 $end
$var wire 1 0 A $end
$var wire 1 1 B $end
$var wire 1 6 Carry $end
$var wire 1 4 Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 4 A $end
$var wire 1 2 B $end
$var wire 1 5 Carry $end
$var wire 1 7 Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 8 A $end
$var wire 1 9 B $end
$var wire 1 : Carry $end
$var wire 1 ; CarryO $end
$var wire 1 < xor1 $end
$var wire 1 = and2 $end
$var wire 1 > and1 $end
$var wire 1 ? Sum $end
$scope module h1 $end
$var wire 1 8 A $end
$var wire 1 9 B $end
$var wire 1 > Carry $end
$var wire 1 < Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 < A $end
$var wire 1 : B $end
$var wire 1 = Carry $end
$var wire 1 ? Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 @ A $end
$var wire 1 A B $end
$var wire 1 B Carry $end
$var wire 1 C CarryO $end
$var wire 1 D xor1 $end
$var wire 1 E and2 $end
$var wire 1 F and1 $end
$var wire 1 G Sum $end
$scope module h1 $end
$var wire 1 @ A $end
$var wire 1 A B $end
$var wire 1 F Carry $end
$var wire 1 D Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 D A $end
$var wire 1 B B $end
$var wire 1 E Carry $end
$var wire 1 G Sum $end
$upscope $end
$upscope $end
$scope module h1 $end
$var wire 1 H A $end
$var wire 1 I B $end
$var wire 1 J Carry $end
$var wire 1 K Sum $end
$upscope $end
$upscope $end
$scope module a2 $end
$var wire 4 L A [3:0] $end
$var wire 4 M B [3:0] $end
$var wire 5 N Y [4:0] $end
$var wire 4 O Carry4 [3:0] $end
$scope module f1 $end
$var wire 1 P A $end
$var wire 1 Q B $end
$var wire 1 R Carry $end
$var wire 1 S CarryO $end
$var wire 1 T xor1 $end
$var wire 1 U and2 $end
$var wire 1 V and1 $end
$var wire 1 W Sum $end
$scope module h1 $end
$var wire 1 P A $end
$var wire 1 Q B $end
$var wire 1 V Carry $end
$var wire 1 T Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 T A $end
$var wire 1 R B $end
$var wire 1 U Carry $end
$var wire 1 W Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 X A $end
$var wire 1 Y B $end
$var wire 1 Z Carry $end
$var wire 1 [ CarryO $end
$var wire 1 \ xor1 $end
$var wire 1 ] and2 $end
$var wire 1 ^ and1 $end
$var wire 1 _ Sum $end
$scope module h1 $end
$var wire 1 X A $end
$var wire 1 Y B $end
$var wire 1 ^ Carry $end
$var wire 1 \ Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 \ A $end
$var wire 1 Z B $end
$var wire 1 ] Carry $end
$var wire 1 _ Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 ` A $end
$var wire 1 a B $end
$var wire 1 b Carry $end
$var wire 1 c CarryO $end
$var wire 1 d xor1 $end
$var wire 1 e and2 $end
$var wire 1 f and1 $end
$var wire 1 g Sum $end
$scope module h1 $end
$var wire 1 ` A $end
$var wire 1 a B $end
$var wire 1 f Carry $end
$var wire 1 d Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 d A $end
$var wire 1 b B $end
$var wire 1 e Carry $end
$var wire 1 g Sum $end
$upscope $end
$upscope $end
$scope module h1 $end
$var wire 1 h A $end
$var wire 1 i B $end
$var wire 1 j Carry $end
$var wire 1 k Sum $end
$upscope $end
$upscope $end
$scope module od1 $end
$var wire 4 l A [3:0] $end
$var wire 1 m AandSum $end
$var wire 4 n B [3:0] $end
$var wire 5 o Y [4:0] $end
$var wire 1 p detect1 $end
$var wire 1 q detect2 $end
$var wire 1 r opC $end
$var wire 2 s opCode [1:0] $end
$var wire 1 ( overflowDetect $end
$var wire 1 t sign1 $end
$var wire 1 u sign2 $end
$var wire 1 v sign3 $end
$var wire 1 w sign4 $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1w
0v
0u
0t
b10 s
1r
1q
1p
b10001 o
b100 n
1m
b101 l
1k
0j
0i
1h
0g
0f
1e
1d
1c
1b
1a
0`
0_
1^
0]
0\
1[
0Z
1Y
1X
0W
0V
0U
0T
0S
0R
0Q
0P
bz100 O
b10001 N
b1100 M
b101 L
0K
1J
1I
1H
1G
0F
0E
1D
0C
0B
0A
1@
1?
0>
0=
0<
0;
1:
09
08
07
06
15
14
13
12
01
10
bz011 /
b1100 .
b1 -
b1011 ,
b1 +
b10001 *
b1100 )
1(
b1011 '
b100 &
b101 %
b100 $
b101 #
b1 "
1!
$end
#5
0Y
0W
0?
0T
0:
1i
0Q
03
02
b1001 M
05
07
bz000 /
0J
b1001 )
b1001 .
1K
04
b10001 "
b10001 +
0b
0!
0(
0H
00
bz000 O
0[
0_
0e
0g
0q
b1000 '
b1000 ,
b10001 *
b10001 N
b10001 o
1k
0^
0\
1f
0d
0m
1v
0h
0X
1`
b111 $
b111 &
b111 n
b1000 #
b1000 %
b1000 L
b1000 l
#10
1B
1;
0Z
1=
0S
0b
1:
0U
0[
13
0T
0^
15
0i
0Q
0Y
1a
12
b1000 M
07
0?
1G
bz111 /
1J
b1000 )
b1000 .
0K
14
1<
0D
0W
b1101 "
b1101 +
0!
0(
1H
10
18
0@
0R
1_
0c
1g
0q
b111 '
b111 ,
bz000 O
0j
b1101 *
b1101 N
b1101 o
1k
1\
0f
1d
0m
1h
1X
0`
b1000 $
b1000 &
b1000 n
b101 #
b101 %
b101 L
b101 l
#15