$date Sun Dec 15 04:15:16 2024 $end $version Icarus Verilog $end $timescale 1s $end $scope module ALUTB $end $var wire 1 ! overflow $end $var wire 4 " Y [3:0] $end $var wire 1 # CarryOUT $end $var reg 4 $ A [3:0] $end $var reg 4 % B [3:0] $end $var reg 1 & CarryIN $end $var reg 3 ' opCodeA [2:0] $end $scope module uut $end $var wire 4 ( A [3:0] $end $var wire 4 ) B [3:0] $end $var wire 1 & CarryIN $end $var wire 3 * opCodeA [2:0] $end $var wire 4 + wireY [3:0] $end $var wire 4 , sub_Y [3:0] $end $var wire 4 - resultX [3:0] $end $var wire 4 . resultO [3:0] $end $var wire 4 / resultA [3:0] $end $var wire 1 ! overflow $end $var wire 8 0 opCode8 [7:0] $end $var wire 4 1 lUOutput2 [3:0] $end $var wire 4 2 lUOutput1 [3:0] $end $var wire 4 3 add_Y [3:0] $end $var wire 4 4 aUtemp2 [3:0] $end $var wire 4 5 aUtemp1 [3:0] $end $var wire 4 6 Y [3:0] $end $var wire 1 # CarryOUT $end $scope module aU $end $var wire 4 7 A [3:0] $end $var wire 4 8 B [3:0] $end $var wire 1 & CarryIN $end $var wire 1 # CarryOUT $end $var wire 2 9 opCode [1:0] $end $var wire 1 ! overflow $end $var wire 4 : sub_Y [3:0] $end $var wire 4 ; subY [3:0] $end $var wire 1 < overflowSUB $end $var wire 1 = overflowADD $end $var wire 4 > add_Y [3:0] $end $var wire 4 ? addY [3:0] $end $var wire 1 @ CarryOUTSUB $end $var wire 1 A CarryOUTADD $end $scope module a1 $end $var wire 4 B A [3:0] $end $var wire 4 C B [3:0] $end $var wire 1 & CarryIN $end $var wire 1 = overflow $end $var wire 4 D Y [3:0] $end $var wire 1 A CarryOUT $end $var wire 4 E Carry4 [3:0] $end $scope module f0 $end $var wire 1 F A $end $var wire 1 G B $end $var wire 1 & Carry $end $var wire 1 H CarryO $end $var wire 1 I xor1 $end $var wire 1 J and2 $end $var wire 1 K and1 $end $var wire 1 L Sum $end $scope module h1 $end $var wire 1 F A $end $var wire 1 G B $end $var wire 1 K Carry $end $var wire 1 I Sum $end $upscope $end $scope module h2 $end $var wire 1 I A $end $var wire 1 & B $end $var wire 1 J Carry $end $var wire 1 L Sum $end $upscope $end $upscope $end $scope module f1 $end $var wire 1 M A $end $var wire 1 N B $end $var wire 1 O Carry $end $var wire 1 P CarryO $end $var wire 1 Q xor1 $end $var wire 1 R and2 $end $var wire 1 S and1 $end $var wire 1 T Sum $end $scope module h1 $end $var wire 1 M A $end $var wire 1 N B $end $var wire 1 S Carry $end $var wire 1 Q Sum $end $upscope $end $scope module h2 $end $var wire 1 Q A $end $var wire 1 O B $end $var wire 1 R Carry $end $var wire 1 T Sum $end $upscope $end $upscope $end $scope module f2 $end $var wire 1 U A $end $var wire 1 V B $end $var wire 1 W Carry $end $var wire 1 X CarryO $end $var wire 1 Y xor1 $end $var wire 1 Z and2 $end $var wire 1 [ and1 $end $var wire 1 \ Sum $end $scope module h1 $end $var wire 1 U A $end $var wire 1 V B $end $var wire 1 [ Carry $end $var wire 1 Y Sum $end $upscope $end $scope module h2 $end $var wire 1 Y A $end $var wire 1 W B $end $var wire 1 Z Carry $end $var wire 1 \ Sum $end $upscope $end $upscope $end $scope module f3 $end $var wire 1 ] A $end $var wire 1 ^ B $end $var wire 1 _ Carry $end $var wire 1 A CarryO $end $var wire 1 ` xor1 $end $var wire 1 a and2 $end $var wire 1 b and1 $end $var wire 1 c Sum $end $scope module h1 $end $var wire 1 ] A $end $var wire 1 ^ B $end $var wire 1 b Carry $end $var wire 1 ` Sum $end $upscope $end $scope module h2 $end $var wire 1 ` A $end $var wire 1 _ B $end $var wire 1 a Carry $end $var wire 1 c Sum $end $upscope $end $upscope $end $scope module od1 $end $var wire 4 d A [3:0] $end $var wire 4 e B [3:0] $end $var wire 1 A CarryOUT $end $var wire 4 f Y [3:0] $end $var wire 1 g addOverflow $end $var wire 1 h detect1 $end $var wire 1 i detect2 $end $var wire 1 j opC $end $var wire 2 k opCode [1:0] $end $var wire 1 = overflowDetect $end $var wire 1 l sign1 $end $var wire 1 m sign2 $end $var wire 1 n sign3 $end $var wire 1 o subOverflow $end $upscope $end $upscope $end $scope module s1 $end $var wire 4 p A [3:0] $end $var wire 4 q B [3:0] $end $var wire 1 & CarryIN $end $var wire 4 r xB [3:0] $end $var wire 1 < overflow $end $var wire 4 s notB [3:0] $end $var wire 4 t Y1 [3:0] $end $var wire 4 u Y [3:0] $end $var wire 1 @ CarryOUT $end $scope module a1 $end $var wire 4 v A [3:0] $end $var wire 4 w B [3:0] $end $var wire 1 x CarryIN $end $var wire 1 y overflow $end $var wire 4 z Y [3:0] $end $var wire 1 { CarryOUT $end $var wire 4 | Carry4 [3:0] $end $scope module f0 $end $var wire 1 } A $end $var wire 1 ~ B $end $var wire 1 x Carry $end $var wire 1 !" CarryO $end $var wire 1 "" xor1 $end $var wire 1 #" and2 $end $var wire 1 $" and1 $end $var wire 1 %" Sum $end $scope module h1 $end $var wire 1 } A $end $var wire 1 ~ B $end $var wire 1 $" Carry $end $var wire 1 "" Sum $end $upscope $end $scope module h2 $end $var wire 1 "" A $end $var wire 1 x B $end $var wire 1 #" Carry $end $var wire 1 %" Sum $end $upscope $end $upscope $end $scope module f1 $end $var wire 1 &" A $end $var wire 1 '" B $end $var wire 1 (" Carry $end $var wire 1 )" CarryO $end $var wire 1 *" xor1 $end $var wire 1 +" and2 $end $var wire 1 ," and1 $end $var wire 1 -" Sum $end $scope module h1 $end $var wire 1 &" A $end $var wire 1 '" B $end $var wire 1 ," Carry $end $var wire 1 *" Sum $end $upscope $end $scope module h2 $end $var wire 1 *" A $end $var wire 1 (" B $end $var wire 1 +" Carry $end $var wire 1 -" Sum $end $upscope $end $upscope $end $scope module f2 $end $var wire 1 ." A $end $var wire 1 /" B $end $var wire 1 0" Carry $end $var wire 1 1" CarryO $end $var wire 1 2" xor1 $end $var wire 1 3" and2 $end $var wire 1 4" and1 $end $var wire 1 5" Sum $end $scope module h1 $end $var wire 1 ." A $end $var wire 1 /" B $end $var wire 1 4" Carry $end $var wire 1 2" Sum $end $upscope $end $scope module h2 $end $var wire 1 2" A $end $var wire 1 0" B $end $var wire 1 3" Carry $end $var wire 1 5" Sum $end $upscope $end $upscope $end $scope module f3 $end $var wire 1 6" A $end $var wire 1 7" B $end $var wire 1 8" Carry $end $var wire 1 { CarryO $end $var wire 1 9" xor1 $end $var wire 1 :" and2 $end $var wire 1 ;" and1 $end $var wire 1 <" Sum $end $scope module h1 $end $var wire 1 6" A $end $var wire 1 7" B $end $var wire 1 ;" Carry $end $var wire 1 9" Sum $end $upscope $end $scope module h2 $end $var wire 1 9" A $end $var wire 1 8" B $end $var wire 1 :" Carry $end $var wire 1 <" Sum $end $upscope $end $upscope $end $scope module od1 $end $var wire 4 =" A [3:0] $end $var wire 4 >" B [3:0] $end $var wire 1 { CarryOUT $end $var wire 4 ?" Y [3:0] $end $var wire 1 @" addOverflow $end $var wire 1 A" detect1 $end $var wire 1 B" detect2 $end $var wire 1 C" opC $end $var wire 2 D" opCode [1:0] $end $var wire 1 y overflowDetect $end $var wire 1 E" sign1 $end $var wire 1 F" sign2 $end $var wire 1 G" sign3 $end $var wire 1 H" subOverflow $end $upscope $end $upscope $end $scope module a2 $end $var wire 4 I" A [3:0] $end $var wire 4 J" B [3:0] $end $var wire 1 & CarryIN $end $var wire 1 K" overflow $end $var wire 4 L" Y [3:0] $end $var wire 1 @ CarryOUT $end $var wire 4 M" Carry4 [3:0] $end $scope module f0 $end $var wire 1 N" A $end $var wire 1 O" B $end $var wire 1 & Carry $end $var wire 1 P" CarryO $end $var wire 1 Q" xor1 $end $var wire 1 R" and2 $end $var wire 1 S" and1 $end $var wire 1 T" Sum $end $scope module h1 $end $var wire 1 N" A $end $var wire 1 O" B $end $var wire 1 S" Carry $end $var wire 1 Q" Sum $end $upscope $end $scope module h2 $end $var wire 1 Q" A $end $var wire 1 & B $end $var wire 1 R" Carry $end $var wire 1 T" Sum $end $upscope $end $upscope $end $scope module f1 $end $var wire 1 U" A $end $var wire 1 V" B $end $var wire 1 W" Carry $end $var wire 1 X" CarryO $end $var wire 1 Y" xor1 $end $var wire 1 Z" and2 $end $var wire 1 [" and1 $end $var wire 1 \" Sum $end $scope module h1 $end $var wire 1 U" A $end $var wire 1 V" B $end $var wire 1 [" Carry $end $var wire 1 Y" Sum $end $upscope $end $scope module h2 $end $var wire 1 Y" A $end $var wire 1 W" B $end $var wire 1 Z" Carry $end $var wire 1 \" Sum $end $upscope $end $upscope $end $scope module f2 $end $var wire 1 ]" A $end $var wire 1 ^" B $end $var wire 1 _" Carry $end $var wire 1 `" CarryO $end $var wire 1 a" xor1 $end $var wire 1 b" and2 $end $var wire 1 c" and1 $end $var wire 1 d" Sum $end $scope module h1 $end $var wire 1 ]" A $end $var wire 1 ^" B $end $var wire 1 c" Carry $end $var wire 1 a" Sum $end $upscope $end $scope module h2 $end $var wire 1 a" A $end $var wire 1 _" B $end $var wire 1 b" Carry $end $var wire 1 d" Sum $end $upscope $end $upscope $end $scope module f3 $end $var wire 1 e" A $end $var wire 1 f" B $end $var wire 1 g" Carry $end $var wire 1 @ CarryO $end $var wire 1 h" xor1 $end $var wire 1 i" and2 $end $var wire 1 j" and1 $end $var wire 1 k" Sum $end $scope module h1 $end $var wire 1 e" A $end $var wire 1 f" B $end $var wire 1 j" Carry $end $var wire 1 h" Sum $end $upscope $end $scope module h2 $end $var wire 1 h" A $end $var wire 1 g" B $end $var wire 1 i" Carry $end $var wire 1 k" Sum $end $upscope $end $upscope $end $scope module od1 $end $var wire 4 l" A [3:0] $end $var wire 4 m" B [3:0] $end $var wire 1 @ CarryOUT $end $var wire 4 n" Y [3:0] $end $var wire 1 o" addOverflow $end $var wire 1 p" detect1 $end $var wire 1 q" detect2 $end $var wire 1 r" opC $end $var wire 2 s" opCode [1:0] $end $var wire 1 K" overflowDetect $end $var wire 1 t" sign1 $end $var wire 1 u" sign2 $end $var wire 1 v" sign3 $end $var wire 1 w" subOverflow $end $upscope $end $upscope $end $scope module od1 $end $var wire 4 x" A [3:0] $end $var wire 4 y" B [3:0] $end $var wire 1 @ CarryOUT $end $var wire 4 z" Y [3:0] $end $var wire 1 {" addOverflow $end $var wire 1 |" detect1 $end $var wire 1 }" detect2 $end $var wire 1 ~" opC $end $var wire 2 !# opCode [1:0] $end $var wire 1 < overflowDetect $end $var wire 1 "# sign1 $end $var wire 1 ## sign2 $end $var wire 1 $# sign3 $end $var wire 1 %# subOverflow $end $upscope $end $upscope $end $upscope $end $scope module lU $end $var wire 4 &# A [3:0] $end $var wire 4 '# B [3:0] $end $var wire 3 (# opCode [2:0] $end $var wire 4 )# xor1 [3:0] $end $var wire 4 *# resultX [3:0] $end $var wire 4 +# resultO [3:0] $end $var wire 4 ,# resultA [3:0] $end $var wire 4 -# or1 [3:0] $end $var wire 4 .# and1 [3:0] $end $upscope $end $scope module opCd $end $var wire 3 /# A [2:0] $end $var wire 1 0# and1 $end $var wire 1 1# and2 $end $var wire 1 2# and3 $end $var wire 1 3# and4 $end $var wire 1 4# notA $end $var wire 1 5# notB $end $var wire 1 6# notC $end $var wire 8 7# opCode [7:0] $end $upscope $end $upscope $end $upscope $end $enddefinitions $end #0 $dumpvars b1 7# 16# 15# 14# 13# 02# 01# 00# b0 /# b0 .# b0 -# b0 ,# b0 +# b0 *# b0 )# b0 (# b0 '# b0 &# 0%# 0$# 0## 1"# b10 !# 1~" 0}" 0|" 0{" b0 z" b0 y" b0 x" 0w" 0v" 0u" 1t" b1 s" 1r" 0q" 1p" 1o" b0 n" b0 m" b0 l" 0k" 0j" 0i" 0h" 0g" 0f" 0e" 0d" 0c" 0b" 0a" 0`" 0_" 0^" 0]" 0\" 0[" 0Z" 0Y" 0X" 0W" 0V" 0U" 0T" 0S" 0R" 0Q" 0P" 0O" 0N" bz000 M" b0 L" 0K" b0 J" b0 I" 0H" 1G" 1F" 0E" b1 D" 1C" 0B" 0A" 0@" b0 ?" b1 >" b1111 =" 0<" 0;" 1:" 19" 18" 07" 16" 05" 04" 13" 12" 11" 10" 0/" 1." 0-" 0," 1+" 1*" 1)" 1(" 0'" 1&" 0%" 1$" 0#" 0"" 1!" 1~ 1} bz111 | 1{ b0 z 0y 0x b1 w b1111 v b0 u b0 t b0 s b1111 r b0 q b0 p 0o 0n 0m 1l b1 k 1j 0i 1h 1g b0 f b0 e b0 d 0c 0b 0a 0` 0_ 0^ 0] 0\ 0[ 0Z 0Y 0X 0W 0V 0U 0T 0S 0R 0Q 0P 0O 0N 0M 0L 0K 0J 0I 0H 0G 0F bz000 E b0 D b0 C b0 B 0A 0@ b0 ? b0 > 0= 0< b0 ; b0 : b1 9 b0 8 b0 7 b0 6 b0 5 b0 4 b0 3 b0 2 b0 1 b1 0 b0 / b0 . b0 - b0 , b0 + b0 * b0 ) b0 ( b0 ' 0& b0 % b0 $ 0# b0 " 0! $end #5 0K" 0q" 0! 0< b1111 " b1111 6 0}" 0u" 0## b1 ; b1 u b1111 + 0y 1p" 1T" 0\" 0d" 0B" b1 t b1 L" b1 n" b1 z" 0k" 1o" b1111 5 1Q" 00" 0Y" 08" 0a" 0h" 1t" 0v" 0(" 1O" 0)" 0V" 01" 0^" 0{ 0f" 1A" 1m b1111 3 b1111 > bz000 | 0!" 1%" 0+" 0-" 03" 05" 0:" b1 s b1 z b1 ?" b1 J" b1 m" 0<" 1@" 0h 0$" 1"" 0*" 02" 09" 1E" 0G" 0F" 1|" 1L 1T 1\ b1111 ? b1111 D b1111 f 1c 0g 0} 0&" 0." 06" 1%# 1I 1Q 1Y 1` 0l 1n b0 r b0 v b0 =" 0"# 1$# b1111 -# b1111 )# 1G 1N 1V 1^ b1111 % b1111 ) b1111 8 b1111 C b1111 e b1111 q b1111 y" b1111 '# #10 1{ 1:" 18" 11" 13" 10" 0g" 0# 1)" 0`" 0@ 1+" 0[" 0c" 0j" 0_" 1(" 0O" 0V" 0^" 0f" 0A" 0y 0X" bz111 | 1!" 0%" 0-" 05" b0 s b0 z b0 ?" b0 J" b0 m" 0<" 0@" 0B" 0Z" b1111 ; b1111 u 0! 1$" 0"" 1*" 12" 19" 0E" 1G" 1F" 0W" 0p" 0K" 0< 1} 1&" 1." 16" bz000 M" 0P" 1T" 1\" 1d" b1111 t b1111 L" b1111 n" b1111 z" 1k" 0o" 0q" 0}" b1111 r b1111 v b1111 =" 0m 0S" 1Q" 1Y" 1a" 1h" 0t" 1v" 0u" 0## 0G 0N 0V 0^ 1F 1M 1U 1] 1N" 1U" 1]" 1e" b0 % b0 ) b0 8 b0 C b0 e b0 q b0 y" b0 '# b1111 $ b1111 ( b1111 7 b1111 B b1111 d b1111 p b1111 I" b1111 l" b1111 x" b1111 &# #15 0K" 1b" 0d" 1i" 0q" 1u" 1## b1111 " b1111 6 1g" 0y 0p" 0! 1`" 0B" 1@ 0k" 0o" b1111 + 0= 1S" 0Q" 00" 0[" 1Y" 08" 0c" 1a" 0j" 1h" 0t" 1v" 1_" 0i 0(" 1O" 0)" 0V" 01" 0^" 0{ 0f" 1A" b1111 5 1X" 0m bz000 | 0!" 1%" 0+" 0-" 03" 05" 0:" b1 s b1 z b1 ?" b1 J" b1 m" 0<" 1@" 1Z" 0\" 1W 1_ 1# 1h 0$" 1"" 0*" 02" 09" 1E" 0G" 0F" 0|" 1O b1111 3 b1111 > 1W" b1 ; b1 u 1P 1T 1X 1\ 1A 1c 1g 0} 0&" 0." 06" 0%# bz111 E 1H bz111 M" 1P" 1K 0I 1S 0Q 1[ 0Y 1b 0` 1l 0n b0 r b0 v b0 =" 1"# 0$# b1111 .# b0 )# 0J b1111 ? b1111 D b1111 f 1L 0R" b1 t b1 L" b1 n" b1 z" 1T" 1G 1N 1V 1^ 1& b1111 % b1111 ) b1111 8 b1111 C b1111 e b1111 q b1111 y" b1111 '# #20 0K" 1f" 0A" 0y 0q" b1001 s b1001 z b1001 ?" b1001 J" b1001 m" 1<" 0@" 0B" 1! b1 ; b1 u 19" 0E" 1G" 0F" 1# 1= 1@ 0p" 16" 0A 1i 1i" b1 t b1 L" b1 n" b1 z" 0k" 0o" b1000 r b1000 v b1000 =" 0b 1m 1h" 0t" 1v" 0u" 0## b111 .# b111 -# 0^ 0] 0e" b111 % b111 ) b111 8 b111 C b111 e b111 q b111 y" b111 '# b111 $ b111 ( b111 7 b111 B b111 d b111 p b111 I" b111 l" b111 x" b111 &# #25 0K" 0q" 1p" 1o" 1F" 0h" 1t" 0v" 1{ 0f" 1:" 0<" 18" 11" 13" 0! b0 " b0 6 10" 0= b0 4 1)" 0i 0# 0u" 0## b0 + 1+" 0m 0@ b0 , b0 : 1(" 0O" 0V" 0^" 0i" 0k" b0 5 bz111 | 1!" 0%" 0-" b0 s b0 z b0 ?" b0 J" b0 m" 05" 0T 0\ 0c 0_" 0g" 1$" 0"" 1*" 12" 0O 0W 0_ 0W" 0X" 0`" b10 9 b0 3 b0 > b0 ; b0 u 1} 1&" 1." 0H 0P bz000 E 0X bz000 M" 0P" 0Z" 0\" 0b" 0d" 06# b10 0 b10 7# b1111 r b1111 v b1111 =" 0K 0S 0[ 0S" 0Q" 0Y" 0a" b0 .# b0 -# b0 ? b0 D b0 f 0L b0 t b0 L" b0 n" b0 z" 0T" 0G 0N 0V 0F 0M 0U 0N" 0U" 0]" b1 ' b1 * b1 /# 0& b0 % b0 ) b0 8 b0 C b0 e b0 q b0 y" b0 '# b0 $ b0 ( b0 7 b0 B b0 d b0 p b0 I" b0 l" b0 x" b0 &# #30 b1 " b1 6 b1 + 0K" b1 4 0q" 0! 0< b1 , b1 : 0}" 0u" 0## b1 ; b1 u 0y 1p" 1T" 0\" 0d" 0B" b1 t b1 L" b1 n" b1 z" 0k" 1o" 1Q" 00" 0Y" 08" 0a" 0h" 1t" 0v" 0(" 1O" 0)" 0V" 01" 0^" 0{ 0f" 1A" 1m bz000 | 0!" 1%" 0+" 0-" 03" 05" 0:" b1 s b1 z b1 ?" b1 J" b1 m" 0<" 1@" 0h 0$" 1"" 0*" 02" 09" 1E" 0G" 0F" 1|" 1L 1T 1\ b1111 ? b1111 D b1111 f 1c 0g 0} 0&" 0." 06" 1%# 1I 1Q 1Y 1` 0l 1n b0 r b0 v b0 =" 0"# 1$# b1111 -# b1111 )# 1G 1N 1V 1^ b1111 % b1111 ) b1111 8 b1111 C b1111 e b1111 q b1111 y" b1111 '# #35 1{ 1:" b1111 " b1111 6 18" 11" b1111 + 13" 10" 0g" 0# b1111 4 1)" 0`" 0@ 1+" 0[" 0c" 0j" 0_" b1111 , b1111 : 1(" 0O" 0V" 0^" 0f" 0A" 0y 0X" bz111 | 1!" 0%" 0-" 05" b0 s b0 z b0 ?" b0 J" b0 m" 0<" 0@" 0B" 0Z" b1111 ; b1111 u 0! 1$" 0"" 1*" 12" 19" 0E" 1G" 1F" 0W" 0p" 0K" 0< 1} 1&" 1." 16" bz000 M" 0P" 1T" 1\" 1d" b1111 t b1111 L" b1111 n" b1111 z" 1k" 0o" 0q" 0}" b1111 r b1111 v b1111 =" 0m 0S" 1Q" 1Y" 1a" 1h" 0t" 1v" 0u" 0## 0G 0N 0V 0^ 1F 1M 1U 1] 1N" 1U" 1]" 1e" b0 % b0 ) b0 8 b0 C b0 e b0 q b0 y" b0 '# b1111 $ b1111 ( b1111 7 b1111 B b1111 d b1111 p b1111 I" b1111 l" b1111 x" b1111 &# #40 0K" b1 " b1 6 1b" 0d" 1i" 0q" 1u" 1## b1 + 1g" 0y 0p" 0! 1`" 0B" 1@ 0k" 0o" b1 4 0= 1S" 0Q" 00" 0[" 1Y" 08" 0c" 1a" 0j" 1h" 0t" 1v" 1_" 0i 0(" 1O" 0)" 0V" 01" 0^" 0{ 0f" 1A" 1X" b1 , b1 : 0m bz000 | 0!" 1%" 0+" 0-" 03" 05" 0:" b1 s b1 z b1 ?" b1 J" b1 m" 0<" 1@" 1Z" 0\" 1W 1_ 1# 1h 0$" 1"" 0*" 02" 09" 1E" 0G" 0F" 0|" 1O 1W" b1 ; b1 u 1P 1T 1X 1\ 1A 1c 1g 0} 0&" 0." 06" 0%# bz111 E 1H bz111 M" 1P" 1K 0I 1S 0Q 1[ 0Y 1b 0` 1l 0n b0 r b0 v b0 =" 1"# 0$# b1111 .# b0 )# 0J b1111 ? b1111 D b1111 f 1L 0R" b1 t b1 L" b1 n" b1 z" 1T" 1G 1N 1V 1^ 1& b1111 % b1111 ) b1111 8 b1111 C b1111 e b1111 q b1111 y" b1111 '# #45 b1001 " b1001 6 b1001 + b1001 4 1K" 1< b1001 , b1001 : 1q" 1}" 1! b1001 ; b1001 u 0h 0= 0@ 1p" 1|" 1a b111 ? b111 D b111 f 0c 0g 0i 0i" b1001 t b1001 L" b1001 n" b1001 z" 1k" 1o" 1%# 0b 1` 0l 1n 0m 0h" 1t" 0v" 1u" 0"# 1$# 1## b111 .# b1000 )# 0] 0e" b111 $ b111 ( b111 7 b111 B b111 d b111 p b111 I" b111 l" b111 x" b111 &# #50