{
 "Device" : "GW2A-18C",
 "Files" : [
  {
   "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
   "Type" : "verilog"
  },
  {
   "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
   "Type" : "verilog"
  },
  {
   "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
   "Type" : "verilog"
  },
  {
   "Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
   "Type" : "verilog"
  }
 ],
 "IncludePath" : [

 ],
 "LoopLimit" : 2000,
 "ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
 "Top" : "",
 "VerilogStd" : "verilog_2001",
 "VhdlStd" : "vhdl_93"
}