$date
	Tue Dec 10 00:01:05 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module muxGateTB $end
$var wire 1 ! Y_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$var reg 1 $ S_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 $ S_i $end
$var wire 1 ! Y_o $end
$var wire 1 % nand2_out $end
$var wire 1 & nand3_out $end
$var wire 1 ' notS $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1'
0&
1%
0$
1#
0"
1!
$end
#10
0!
1&
0#
1"
#20
0!
0'
1&
1$
1#
0"
#40