$date
	Tue Jul  9 19:50:51 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module test2Tb $end
$var wire 7 ! b [6:0] $end
$var reg 4 " a [3:0] $end
$scope module uut $end
$var wire 4 # a [3:0] $end
$var wire 7 $ b [6:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b111110 $
b101 #
b101 "
b111110 !
$end
#10