Synthesis Messages

Report Title GowinSynthesis Report
Design File \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 Education (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Sat Jan 18 22:12:34 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module bttn
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.353s, Peak memory usage = 391.969MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 391.969MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 391.969MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 391.969MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 391.969MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 391.969MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 391.969MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 391.969MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 391.969MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 391.969MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 391.969MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 391.969MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 391.969MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.081s, Peak memory usage = 391.969MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 391.969MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 25
I/O Buf 25
    IBUF 13
    OBUF 12
LUT 137
    LUT2 20
    LUT3 35
    LUT4 82

Resource Utilization Summary

Resource Usage Utilization
Logic 137(137 LUT, 0 ALU) / 20736 <1%
Register 0 / 16173 0%
  --Register as Latch 0 / 16173 0%
  --Register as FF 0 / 16173 0%
BSRAM 0 / 46 0%