Power Messages

Report Title Power Analysis Report
Design File \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst
Timing Constraints File ---
Tool Version V1.9.9.03 Education (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Fri Jul 5 01:48:01 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade Commercial
Process Typical
Ambient Temperature 25.000
Use Custom Theta JA false
Heat Sink None
Air Flow LFM_0
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Related Vcd File
Related Saif File
Filter Glitches false
Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125

Power Summary

Power Information:

Total Power (mW) 121.872
Quiescent Power (mW) 120.982
Dynamic Power (mW) 0.890

Thermal Information:

Junction Temperature 28.902
Theta JA 32.020
Max Allowed Ambient Temperature 81.098

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 0.158 69.996 70.154
VCCX 3.300 0.158 15.000 50.020
VCCIO12 1.200 0.118 0.429 0.656
VCCIO18 1.800 0.039 0.540 1.042

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
IO 3.178 2.288 7.143

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
ledTest 0.000 0.000(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
NO CLOCK DOMAIN 0.000 0.000