$date
	Fri Jul  5 05:10:51 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module lab4tb $end
$var wire 4 ! s2 [3:0] $end
$var reg 9 " s1 [8:0] $end
$scope module uut $end
$var wire 9 # signal [8:0] $end
$var reg 4 $ S [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b110 $
b100101001 #
b100101001 "
b110 !
$end
#10
b100 !
b100 $
b10101001 "
b10101001 #
#20
b1 !
b1 $
b1101001 "
b1101001 #
#30
b101 !
b101 $
b101001 "
b101001 #
#40