$date
	Sun Dec  1 02:50:52 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module notGateTB $end
$var wire 1 ! B $end
$var reg 1 " A $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 ! B $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0"
1!
$end
#10
0!
1"
#20