$date
	Sun Dec  1 02:41:57 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module andGateTB $end
$var wire 1 ! Y $end
$var reg 1 " A $end
$var reg 1 # B $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 # B $end
$var wire 1 ! Y $end
$var wire 1 $ tempOut $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1$
0#
0"
0!
$end
#10
1#
#20
0#
1"
#30
1!
0$
1#
#40