$date
	Mon Jul  8 05:12:15 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module timerTB $end
$var wire 6 ! count [5:0] $end
$var reg 1 " clock $end
$var reg 3 # counter [2:0] $end
$var reg 1 $ gate $end
$var reg 1 % reset $end
$var reg 1 & way $end
$scope module uut $end
$var wire 1 " clock $end
$var wire 3 ' counter [2:0] $end
$var wire 1 $ gate $end
$var wire 1 % reset $end
$var wire 1 & way $end
$var reg 6 ( count [5:0] $end
$var reg 6 ) countReg [5:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b101011 )
b101011 (
b10 '
1&
1%
1$
b10 #
0"
b101011 !
$end
#5
b0 !
b0 (
b0 )
1"
#10
0"
#15
1"
#20
0"
#25
1"
#30
0"
#35
1"
#40
0"
#45
1"
#50
0"
#55
1"
#60
0"
#65
1"
#70
0"
#75
1"
#80
0"
#85
1"
#90
0"
#95
1"
#100
0"
#105
1"
#110
0"
#115
1"
#120
0"
#125
1"
#130
0"
#135
1"
#140
0"
#145
1"
#150
0"
#155
1"
#160
0"
#165
1"
#170
0"
#175
1"
#180
0"
#185
1"
#190
0"
#195
1"
#200
0"