$date
	Thu Dec 12 01:03:03 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module bit3AdderTB $end
$var wire 4 ! Sum [3:0] $end
$var reg 3 " A [2:0] $end
$var reg 3 # B [2:0] $end
$scope module uut $end
$var wire 3 $ A [2:0] $end
$var wire 3 % B [2:0] $end
$var wire 4 & Sum [3:0] $end
$var wire 3 ' Carry3 [2:0] $end
$scope module f1 $end
$var wire 1 ( A $end
$var wire 1 ) B $end
$var wire 1 * CarryIn $end
$var wire 1 + CarryOut $end
$var wire 1 , Sum $end
$var wire 1 - AxorB $end
$var wire 1 . AandB $end
$var wire 1 / ABandCIn $end
$scope module h1 $end
$var wire 1 ( A $end
$var wire 1 ) B $end
$var wire 1 . CarryOut $end
$var wire 1 - Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 - A $end
$var wire 1 * B $end
$var wire 1 / CarryOut $end
$var wire 1 , Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 0 A $end
$var wire 1 1 B $end
$var wire 1 2 CarryIn $end
$var wire 1 3 CarryOut $end
$var wire 1 4 Sum $end
$var wire 1 5 AxorB $end
$var wire 1 6 AandB $end
$var wire 1 7 ABandCIn $end
$scope module h1 $end
$var wire 1 0 A $end
$var wire 1 1 B $end
$var wire 1 6 CarryOut $end
$var wire 1 5 Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 5 A $end
$var wire 1 2 B $end
$var wire 1 7 CarryOut $end
$var wire 1 4 Sum $end
$upscope $end
$upscope $end
$scope module h1 $end
$var wire 1 8 A $end
$var wire 1 9 B $end
$var wire 1 : CarryOut $end
$var wire 1 ; Sum $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0;
0:
09
08
07
06
05
04
03
02
01
00
0/
0.
0-
0,
0+
0*
0)
0(
bz00 '
b0 &
b0 %
b0 $
b0 #
b0 "
b0 !
$end
#10
b1 !
b1 &
1;
19
b1 #
b1 %
#20
1,
1*
b10 !
b10 &
0;
bz01 '
1:
18
b1 "
b1 $
#30
14
b100 !
b100 &
0,
12
0*
1+
bz10 '
0:
1.
09
1)
08
1(
b10 #
b10 %
b10 "
b10 $
#40
b101 !
b101 &
1;
19
b11 #
b11 %
#50
13
04
17
b1000 !
b1000 &
0;
15
09
10
b10 #
b10 %
b110 "
b110 $
#60
02
04
07
bz00 '
0+
05
16
b1001 !
b1001 &
1;
0.
0)
11
18
0(
b100 #
b100 %
b101 "
b101 $
#70
b1011 !
b1011 &
1,
1-
1(
b111 "
b111 $
#80
14
12
b1101 !
b1101 &
0,
bz10 '
1+
0-
1.
1)
b110 #
b110 %
#90
1,
1*
b1110 !
b1110 &
0;
bz11 '
1:
19
b111 #
b111 %
#100