$date
	Tue Oct  8 10:23:08 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module halfaddertb $end
$var wire 1 ! S $end
$var wire 1 " C $end
$var reg 1 # A $end
$var reg 1 $ B $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 " C $end
$var wire 1 ! S $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0$
0#
0"
0!
$end
#10
1!
1$
#20
0$
1#
#30
0!
1"
1$
#40