| Report Title |
Power Analysis Report |
| Design File |
C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg |
| Physical Constraints File |
--- |
| Timing Constraints File |
--- |
| Tool Version |
V1.9.9.02 |
| Part Number |
GW2A-LV18PG256C8/I7 |
| Device |
GW2A-18 |
| Device Version |
C |
| Created Time |
Sat May 4 01:07:45 2024
|
| Legal Announcement |
Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
92.439 |
| Quiescent Power (mW) |
91.608 |
| Dynamic Power (mW) |
0.832 |
| Junction Temperature |
27.960 |
| Theta JA |
32.020 |
| Max Allowed Ambient Temperature |
82.040 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.000 |
0.158 |
61.510 |
61.668 |
| VCCX |
2.500 |
0.158 |
11.364 |
28.803 |
| VCCIO18 |
1.800 |
0.155 |
0.938 |
1.968 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| IO |
3.335
| 2.503
| 6.250
|
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
| mult2bit |
0.000 |
0.000(0.000) |
| mult2bit/h0/ |
0.000 |
0.000(0.000) |
| mult2bit/h1/ |
0.000 |
0.000(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| NO CLOCK DOMAIN |
0.000 |
0.000 |