{
 "Device" : "GW2A-18C",
 "Files" : [
  {
   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
   "Type" : "verilog"
  }
 ],
 "IncludePath" : [

 ],
 "LoopLimit" : 2000,
 "ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/impl/temp/rtl_parser.result",
 "Top" : "",
 "VerilogStd" : "verilog_2001",
 "VhdlStd" : "vhdl_93"
}