$date
	Tue Dec 10 00:39:27 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module andSixTGateTB $end
$var wire 16 ! Y_o [15:0] $end
$var reg 16 " A_i [15:0] $end
$var reg 16 # B_i [15:0] $end
$scope module uut $end
$var wire 16 $ A_i [15:0] $end
$var wire 16 % B_i [15:0] $end
$var wire 16 & Y_o [15:0] $end
$scope module a0 $end
$var wire 1 ' A_i $end
$var wire 1 ( B_i $end
$var wire 1 ) Y_o $end
$var wire 1 * nand_out $end
$upscope $end
$scope module a1 $end
$var wire 1 + A_i $end
$var wire 1 , B_i $end
$var wire 1 - Y_o $end
$var wire 1 . nand_out $end
$upscope $end
$scope module a10 $end
$var wire 1 / A_i $end
$var wire 1 0 B_i $end
$var wire 1 1 Y_o $end
$var wire 1 2 nand_out $end
$upscope $end
$scope module a11 $end
$var wire 1 3 A_i $end
$var wire 1 4 B_i $end
$var wire 1 5 Y_o $end
$var wire 1 6 nand_out $end
$upscope $end
$scope module a12 $end
$var wire 1 7 A_i $end
$var wire 1 8 B_i $end
$var wire 1 9 Y_o $end
$var wire 1 : nand_out $end
$upscope $end
$scope module a13 $end
$var wire 1 ; A_i $end
$var wire 1 < B_i $end
$var wire 1 = Y_o $end
$var wire 1 > nand_out $end
$upscope $end
$scope module a14 $end
$var wire 1 ? A_i $end
$var wire 1 @ B_i $end
$var wire 1 A Y_o $end
$var wire 1 B nand_out $end
$upscope $end
$scope module a15 $end
$var wire 1 C A_i $end
$var wire 1 D B_i $end
$var wire 1 E Y_o $end
$var wire 1 F nand_out $end
$upscope $end
$scope module a2 $end
$var wire 1 G A_i $end
$var wire 1 H B_i $end
$var wire 1 I Y_o $end
$var wire 1 J nand_out $end
$upscope $end
$scope module a3 $end
$var wire 1 K A_i $end
$var wire 1 L B_i $end
$var wire 1 M Y_o $end
$var wire 1 N nand_out $end
$upscope $end
$scope module a4 $end
$var wire 1 O A_i $end
$var wire 1 P B_i $end
$var wire 1 Q Y_o $end
$var wire 1 R nand_out $end
$upscope $end
$scope module a5 $end
$var wire 1 S A_i $end
$var wire 1 T B_i $end
$var wire 1 U Y_o $end
$var wire 1 V nand_out $end
$upscope $end
$scope module a6 $end
$var wire 1 W A_i $end
$var wire 1 X B_i $end
$var wire 1 Y Y_o $end
$var wire 1 Z nand_out $end
$upscope $end
$scope module a7 $end
$var wire 1 [ A_i $end
$var wire 1 \ B_i $end
$var wire 1 ] Y_o $end
$var wire 1 ^ nand_out $end
$upscope $end
$scope module a8 $end
$var wire 1 _ A_i $end
$var wire 1 ` B_i $end
$var wire 1 a Y_o $end
$var wire 1 b nand_out $end
$upscope $end
$scope module a9 $end
$var wire 1 c A_i $end
$var wire 1 d B_i $end
$var wire 1 e Y_o $end
$var wire 1 f nand_out $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1f
0e
0d
0c
1b
0a
0`
0_
1^
0]
0\
0[
1Z
0Y
0X
0W
1V
0U
0T
0S
1R
0Q
0P
0O
1N
0M
0L
0K
1J
0I
0H
0G
1F
0E
0D
0C
1B
0A
0@
0?
1>
0=
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0;
1:
09
08
07
16
05
04
03
12
01
00
0/
1.
0-
0,
0+
1*
0)
0(
0'
b0 &
b0 %
b0 $
b0 #
b0 "
b0 !
$end
#10
1(
b1 #
b1 %
#20
b1 !
b1 &
1)
0*
1'
b1 "
b1 $
#30
b0 !
b0 &
0)
1*
0(
0'
1W
b0 #
b0 %
b1000000 "
b1000000 $
#40
b1000000 !
b1000000 &
1Y
0Z
1X
b1000000 #
b1000000 %
#50
b0 !
b0 &
0Y
1Z
0X
1d
0W
b1000000000 #
b1000000000 %
b0 "
b0 $
#60
b1000000000 !
b1000000000 &
1e
0f
1c
b1000000000 "
b1000000000 $
#70
1)
1-
1I
1M
1Q
1U
1Y
1]
1a
11
15
19
1=
1A
b1111111111111111 !
b1111111111111111 &
1E
0*
0.
0J
0N
0R
0V
0Z
0^
0b
02
06
0:
0>
0B
0F
1(
1,
1H
1L
1P
1T
1X
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10
14
18
1<
1@
1D
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1+
1G
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1O
1S
1W
1[
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13
17
1;
1?
1C
b1111111111111111 #
b1111111111111111 %
b1111111111111111 "
b1111111111111111 $
#80