verilog
This commit is contained in:
60
tests/a.out
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60
tests/a.out
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#! /c/Source/iverilog-install/bin/vvp
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:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "C:\iverilog\lib\ivl\system.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
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:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
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:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
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S_0000014670375350 .scope module, "hello" "hello" 2 1;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "C";
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.port_info 3 /OUTPUT 1 "D";
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o0000014670376fd8 .functor BUFZ 1, C4<z>; HiZ drive
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o0000014670377008 .functor BUFZ 1, C4<z>; HiZ drive
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L_0000014670326ea0 .functor AND 1, o0000014670376fd8, o0000014670377008, C4<1>, C4<1>;
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L_0000014670327320 .functor XOR 1, o0000014670376fd8, o0000014670377008, C4<0>, C4<0>;
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v00000146703270e0_0 .net "A", 0 0, o0000014670376fd8; 0 drivers
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v0000014670375670_0 .net "B", 0 0, o0000014670377008; 0 drivers
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v0000014670375710_0 .net "C", 0 0, L_0000014670327320; 1 drivers
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v000001467032ee60_0 .net "D", 0 0, L_0000014670326ea0; 1 drivers
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S_00000146703754e0 .scope module, "hello_tb" "hello_tb" 3 1;
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.timescale 0 0;
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v000001467032ef00_0 .var "A", 0 0;
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v000001467032b870_0 .var "B", 0 0;
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.scope S_00000146703754e0;
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T_0 ;
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%vpi_call 3 8 "$dumpfile", "dmp.vcd" {0 0 0};
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%vpi_call 3 9 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001467032ef00_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001467032b870_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001467032ef00_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001467032b870_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001467032ef00_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001467032b870_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001467032ef00_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001467032b870_0, 0, 1;
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%delay 10, 0;
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%vpi_call 3 14 "$finish" {0 0 0};
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%end;
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.thread T_0;
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# The file index is used to find the file name in the following table.
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:file_names 4;
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"N/A";
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"<interactive>";
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"hello.v";
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"hello_tb.v";
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40
tests/dmp.vcd
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40
tests/dmp.vcd
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$date
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Sat Apr 06 17:40:37 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module hello $end
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$var wire 1 ! A $end
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$var wire 1 " B $end
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$var wire 1 # C $end
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$var wire 1 $ D $end
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$upscope $end
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$scope module hello_tb $end
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$var reg 1 % A $end
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$var reg 1 & B $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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0&
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0%
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x$
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x#
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z"
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z!
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$end
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#10
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1&
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#20
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0&
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1%
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#30
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1&
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#40
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9
tests/hello.v
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9
tests/hello.v
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module hello(
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input wire A, B,
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output wire C, D
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);
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and(D, A, B);
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xor(C, A, B);
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endmodule
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17
tests/hello_tb.v
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17
tests/hello_tb.v
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module hello_tb();
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reg A;
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reg B;
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wire C, D;
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initial begin
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$dumpfile("dmp.vcd");
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$dumpvars;
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A = 0; B = 0; #10;
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A = 0; B = 1; #10;
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A = 1; B = 0; #10;
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A = 1; B = 1; #10;
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$finish;
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end
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endmodule
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65
tests/test/a.out
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65
tests/test/a.out
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#! /c/Source/iverilog-install/bin/vvp
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:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "C:\iverilog\lib\ivl\system.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
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:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
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:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
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S_000001c04a3a6760 .scope module, "tb" "tb" 2 1;
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.timescale 0 0;
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v000001c04a3a6b20_0 .var "r1", 0 0;
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v000001c04a51ba60_0 .var "r2", 0 0;
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v000001c04a51bb00_0 .net "w1", 0 0, L_000001c04a518b00; 1 drivers
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v000001c04a51bba0_0 .net "w2", 0 0, L_000001c04a518d50; 1 drivers
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v000001c04a51bc40_0 .net "w3", 0 0, L_000001c04a517170; 1 drivers
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S_000001c04a3a68f0 .scope module, "uut" "test" 2 6, 3 1 0, S_000001c04a3a6760;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "LED1";
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.port_info 3 /OUTPUT 1 "LED2";
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.port_info 4 /OUTPUT 1 "LED3";
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L_000001c04a518b00 .functor BUFZ 1, v000001c04a3a6b20_0, C4<0>, C4<0>, C4<0>;
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L_000001c04a518d50 .functor BUFZ 1, v000001c04a51ba60_0, C4<0>, C4<0>, C4<0>;
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L_000001c04a517170 .functor OR 1, v000001c04a3a6b20_0, v000001c04a51ba60_0, C4<0>, C4<0>;
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v000001c04a519860_0 .net "A", 0 0, v000001c04a3a6b20_0; 1 drivers
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v000001c04a516ec0_0 .net "B", 0 0, v000001c04a51ba60_0; 1 drivers
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v000001c04a518cb0_0 .net "LED1", 0 0, L_000001c04a518b00; alias, 1 drivers
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v000001c04a518a60_0 .net "LED2", 0 0, L_000001c04a518d50; alias, 1 drivers
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v000001c04a3a6a80_0 .net "LED3", 0 0, L_000001c04a517170; alias, 1 drivers
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.scope S_000001c04a3a6760;
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T_0 ;
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%vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0};
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%vpi_call 2 18 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001c04a3a6b20_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001c04a51ba60_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001c04a3a6b20_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001c04a51ba60_0, 0, 1;
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%delay 10, 0;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001c04a3a6b20_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v000001c04a51ba60_0, 0, 1;
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%delay 10, 0;
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%vpi_call 2 22 "$display", v000001c04a51bc40_0 {0 0 0};
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001c04a3a6b20_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v000001c04a51ba60_0, 0, 1;
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%delay 10, 0;
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%vpi_call 2 24 "$display", v000001c04a51bc40_0 {0 0 0};
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%end;
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.thread T_0;
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# The file index is used to find the file name in the following table.
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:file_names 4;
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"N/A";
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"<interactive>";
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"tb.v";
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"test.v";
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48
tests/test/dmp.vcd
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48
tests/test/dmp.vcd
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$date
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Sat Apr 06 17:45:47 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module tb $end
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$var wire 1 ! w3 $end
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$var wire 1 " w2 $end
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$var wire 1 # w1 $end
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$var reg 1 $ r1 $end
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$var reg 1 % r2 $end
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$scope module uut $end
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$var wire 1 $ A $end
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$var wire 1 % B $end
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$var wire 1 # LED1 $end
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$var wire 1 " LED2 $end
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$var wire 1 ! LED3 $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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0%
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0$
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0#
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0"
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0!
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$end
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#10
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1!
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1"
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1%
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#20
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0"
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0%
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1#
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1$
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#30
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1"
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1%
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#40
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29
tests/test/tb.v
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29
tests/test/tb.v
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module tb();
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reg r1, r2;
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wire w1, w2, w3;
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test uut(
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.A(r1),
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.B(r2),
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.LED1(w1),
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.LED2(w2),
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.LED3(w3)
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);
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// test uut(r1, r2, w1, w2, w3);
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initial begin
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$dumpfile("dmp.vcd");
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$dumpvars;
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r1 = 0; r2 = 0; #10;
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r1 = 0; r2 = 1; #10;
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r1 = 1; r2 = 0; #10;
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$display(w3);
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r1 = 1; r2 = 1; #10;
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$display(w3);
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end
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endmodule
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20
tests/test/test.v
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20
tests/test/test.v
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module test(
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input A,
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input B,
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output LED1,
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output LED2,
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output LED3
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);
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assign LED1 = A;
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assign LED2 = B;
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assign LED3 = A | B;
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/*
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buf(LED1, A);
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buf(LED2, B);
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and(LED3, A, B);
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*/
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endmodule
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