verilog
This commit is contained in:
217
labs/lab3/src/3bit
Normal file
217
labs/lab3/src/3bit
Normal file
@ -0,0 +1,217 @@
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#! /c/Source/iverilog-install/bin/vvp
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:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "C:\iverilog\lib\ivl\system.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
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:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
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:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
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S_00000154a426eaa0 .scope module, "tb" "tb" 2 1;
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.timescale 0 0;
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v00000154a4316c30_0 .var "A", 2 0;
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v00000154a4316370_0 .var "B", 2 0;
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v00000154a4317770_0 .net "C", 3 0, L_00000154a43162d0; 1 drivers
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S_00000154a426ec30 .scope module, "uut" "Adder3Bit" 2 5, 3 1 0, S_00000154a426eaa0;
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.timescale 0 0;
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.port_info 0 /INPUT 3 "A";
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.port_info 1 /INPUT 3 "B";
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.port_info 2 /OUTPUT 4 "C";
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v00000154a4316230_0 .net "A", 2 0, v00000154a4316c30_0; 1 drivers
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v00000154a43173b0_0 .net "B", 2 0, v00000154a4316370_0; 1 drivers
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v00000154a4317450_0 .net "C", 3 0, L_00000154a43162d0; alias, 1 drivers
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v00000154a4316050_0 .net "c1", 0 0, L_00000154a42aabe0; 1 drivers
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v00000154a43174f0_0 .net "c2", 0 0, L_00000154a42ab200; 1 drivers
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L_00000154a4315fb0 .part v00000154a4316c30_0, 0, 1;
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L_00000154a4315b50 .part v00000154a4316370_0, 0, 1;
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L_00000154a4316190 .part v00000154a4316c30_0, 1, 1;
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L_00000154a4317590 .part v00000154a4316370_0, 1, 1;
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L_00000154a4317630 .part v00000154a4316c30_0, 2, 1;
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L_00000154a4316a50 .part v00000154a4316370_0, 2, 1;
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L_00000154a43162d0 .concat8 [ 1 1 1 1], L_00000154a42aa8d0, L_00000154a42ab580, L_00000154a42ab660, L_00000154a42aad30;
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S_00000154a426d820 .scope module, "a0" "halfAdder" 3 8, 4 1 0, S_00000154a426ec30;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "S";
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.port_info 3 /OUTPUT 1 "C";
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L_00000154a42aa8d0 .functor XOR 1, L_00000154a4315fb0, L_00000154a4315b50, C4<0>, C4<0>;
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L_00000154a42aabe0 .functor AND 1, L_00000154a4315fb0, L_00000154a4315b50, C4<1>, C4<1>;
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v00000154a42aa140_0 .net "A", 0 0, L_00000154a4315fb0; 1 drivers
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v00000154a42a9c40_0 .net "B", 0 0, L_00000154a4315b50; 1 drivers
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v00000154a42aa000_0 .net "C", 0 0, L_00000154a42aabe0; alias, 1 drivers
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v00000154a42a9880_0 .net "S", 0 0, L_00000154a42aa8d0; 1 drivers
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S_00000154a426d9b0 .scope module, "a1" "fullAdder" 3 10, 5 1 0, S_00000154a426ec30;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Z";
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.port_info 3 /OUTPUT 1 "S";
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.port_info 4 /OUTPUT 1 "C";
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L_00000154a42ab200 .functor OR 1, L_00000154a42aab70, L_00000154a42aa940, C4<0>, C4<0>;
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v00000154a42a99c0_0 .net "A", 0 0, L_00000154a4316190; 1 drivers
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v00000154a42aa6e0_0 .net "B", 0 0, L_00000154a4317590; 1 drivers
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v00000154a42aa320_0 .net "C", 0 0, L_00000154a42ab200; alias, 1 drivers
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v00000154a42aa500_0 .net "S", 0 0, L_00000154a42ab580; 1 drivers
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v00000154a42a9b00_0 .net "W0", 0 0, L_00000154a42ab510; 1 drivers
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v00000154a42aa640_0 .net "W1", 0 0, L_00000154a42aab70; 1 drivers
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v00000154a42a9d80_0 .net "W2", 0 0, L_00000154a42aa940; 1 drivers
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v00000154a42a9ec0_0 .net "Z", 0 0, L_00000154a42aabe0; alias, 1 drivers
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S_00000154a426c910 .scope module, "h0" "halfAdder" 5 7, 4 1 0, S_00000154a426d9b0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "S";
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.port_info 3 /OUTPUT 1 "C";
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L_00000154a42ab510 .functor XOR 1, L_00000154a4316190, L_00000154a4317590, C4<0>, C4<0>;
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L_00000154a42aab70 .functor AND 1, L_00000154a4316190, L_00000154a4317590, C4<1>, C4<1>;
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v00000154a42aa0a0_0 .net "A", 0 0, L_00000154a4316190; alias, 1 drivers
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v00000154a42a9a60_0 .net "B", 0 0, L_00000154a4317590; alias, 1 drivers
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v00000154a42aa1e0_0 .net "C", 0 0, L_00000154a42aab70; alias, 1 drivers
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v00000154a42aa280_0 .net "S", 0 0, L_00000154a42ab510; alias, 1 drivers
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S_00000154a426caa0 .scope module, "h1" "halfAdder" 5 8, 4 1 0, S_00000154a426d9b0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "S";
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.port_info 3 /OUTPUT 1 "C";
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L_00000154a42ab580 .functor XOR 1, L_00000154a42ab510, L_00000154a42aabe0, C4<0>, C4<0>;
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L_00000154a42aa940 .functor AND 1, L_00000154a42ab510, L_00000154a42aabe0, C4<1>, C4<1>;
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v00000154a42a97e0_0 .net "A", 0 0, L_00000154a42ab510; alias, 1 drivers
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v00000154a42a9ce0_0 .net "B", 0 0, L_00000154a42aabe0; alias, 1 drivers
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v00000154a42a9920_0 .net "C", 0 0, L_00000154a42aa940; alias, 1 drivers
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v00000154a42aa460_0 .net "S", 0 0, L_00000154a42ab580; alias, 1 drivers
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S_00000154a4282990 .scope module, "a2" "fullAdder" 3 11, 5 1 0, S_00000154a426ec30;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Z";
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.port_info 3 /OUTPUT 1 "S";
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||||
.port_info 4 /OUTPUT 1 "C";
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L_00000154a42aad30 .functor OR 1, L_00000154a42ab3c0, L_00000154a42aa9b0, C4<0>, C4<0>;
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||||
v00000154a4316910_0 .net "A", 0 0, L_00000154a4317630; 1 drivers
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v00000154a43160f0_0 .net "B", 0 0, L_00000154a4316a50; 1 drivers
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||||
v00000154a4317270_0 .net "C", 0 0, L_00000154a42aad30; 1 drivers
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||||
v00000154a4316ff0_0 .net "S", 0 0, L_00000154a42ab660; 1 drivers
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v00000154a4316b90_0 .net "W0", 0 0, L_00000154a42ab350; 1 drivers
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v00000154a43171d0_0 .net "W1", 0 0, L_00000154a42ab3c0; 1 drivers
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||||
v00000154a4317310_0 .net "W2", 0 0, L_00000154a42aa9b0; 1 drivers
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v00000154a43176d0_0 .net "Z", 0 0, L_00000154a42ab200; alias, 1 drivers
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||||
S_00000154a4282b20 .scope module, "h0" "halfAdder" 5 7, 4 1 0, S_00000154a4282990;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "S";
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.port_info 3 /OUTPUT 1 "C";
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L_00000154a42ab350 .functor XOR 1, L_00000154a4317630, L_00000154a4316a50, C4<0>, C4<0>;
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L_00000154a42ab3c0 .functor AND 1, L_00000154a4317630, L_00000154a4316a50, C4<1>, C4<1>;
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v00000154a42a9e20_0 .net "A", 0 0, L_00000154a4317630; alias, 1 drivers
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v00000154a42aa5a0_0 .net "B", 0 0, L_00000154a4316a50; alias, 1 drivers
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v00000154a4316870_0 .net "C", 0 0, L_00000154a42ab3c0; alias, 1 drivers
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v00000154a4315c90_0 .net "S", 0 0, L_00000154a42ab350; alias, 1 drivers
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S_00000154a4282cb0 .scope module, "h1" "halfAdder" 5 8, 4 1 0, S_00000154a4282990;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "S";
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.port_info 3 /OUTPUT 1 "C";
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L_00000154a42ab660 .functor XOR 1, L_00000154a42ab350, L_00000154a42ab200, C4<0>, C4<0>;
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L_00000154a42aa9b0 .functor AND 1, L_00000154a42ab350, L_00000154a42ab200, C4<1>, C4<1>;
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v00000154a4315ab0_0 .net "A", 0 0, L_00000154a42ab350; alias, 1 drivers
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||||
v00000154a4316730_0 .net "B", 0 0, L_00000154a42ab200; alias, 1 drivers
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v00000154a43169b0_0 .net "C", 0 0, L_00000154a42aa9b0; alias, 1 drivers
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v00000154a4317130_0 .net "S", 0 0, L_00000154a42ab660; alias, 1 drivers
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.scope S_00000154a426eaa0;
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T_0 ;
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%vpi_call 2 8 "$dumpfile", "dmp.vcd" {0 0 0};
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%vpi_call 2 9 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 3;
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%store/vec4 v00000154a4316c30_0, 0, 3;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v00000154a4316370_0, 0, 3;
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%delay 10, 0;
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%pushi/vec4 1, 0, 3;
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||||
%store/vec4 v00000154a4316c30_0, 0, 3;
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||||
%pushi/vec4 6, 0, 3;
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%store/vec4 v00000154a4316370_0, 0, 3;
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||||
%delay 10, 0;
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||||
%pushi/vec4 2, 0, 3;
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||||
%store/vec4 v00000154a4316c30_0, 0, 3;
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||||
%pushi/vec4 5, 0, 3;
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||||
%store/vec4 v00000154a4316370_0, 0, 3;
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||||
%delay 10, 0;
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||||
%pushi/vec4 3, 0, 3;
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||||
%store/vec4 v00000154a4316c30_0, 0, 3;
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||||
%pushi/vec4 4, 0, 3;
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||||
%store/vec4 v00000154a4316370_0, 0, 3;
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||||
%delay 10, 0;
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||||
%pushi/vec4 4, 0, 3;
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||||
%store/vec4 v00000154a4316c30_0, 0, 3;
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||||
%pushi/vec4 3, 0, 3;
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||||
%store/vec4 v00000154a4316370_0, 0, 3;
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||||
%delay 10, 0;
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||||
%pushi/vec4 5, 0, 3;
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||||
%store/vec4 v00000154a4316c30_0, 0, 3;
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||||
%pushi/vec4 2, 0, 3;
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||||
%store/vec4 v00000154a4316370_0, 0, 3;
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||||
%delay 10, 0;
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||||
%pushi/vec4 6, 0, 3;
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||||
%store/vec4 v00000154a4316c30_0, 0, 3;
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||||
%pushi/vec4 1, 0, 3;
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||||
%store/vec4 v00000154a4316370_0, 0, 3;
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||||
%delay 10, 0;
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||||
%pushi/vec4 7, 0, 3;
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||||
%store/vec4 v00000154a4316c30_0, 0, 3;
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||||
%pushi/vec4 0, 0, 3;
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||||
%store/vec4 v00000154a4316370_0, 0, 3;
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||||
%delay 10, 0;
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||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 6;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\tb.v";
|
||||
".\Adder3Bit.v";
|
||||
".\halfAdder.v";
|
||||
".\fullAdder.v";
|
||||
142
labs/lab3/src/3dmp.vcd
Normal file
142
labs/lab3/src/3dmp.vcd
Normal file
@ -0,0 +1,142 @@
|
||||
$date
|
||||
Sat May 04 01:15:09 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module fullAdder $end
|
||||
$var wire 1 ! A $end
|
||||
$var wire 1 " B $end
|
||||
$var wire 1 # C $end
|
||||
$var wire 1 $ Z $end
|
||||
$var wire 1 % W2 $end
|
||||
$var wire 1 & W1 $end
|
||||
$var wire 1 ' W0 $end
|
||||
$var wire 1 ( S $end
|
||||
$scope module h0 $end
|
||||
$var wire 1 ! A $end
|
||||
$var wire 1 " B $end
|
||||
$var wire 1 & C $end
|
||||
$var wire 1 ' S $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 ' A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 % C $end
|
||||
$var wire 1 ( S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module mtb $end
|
||||
$var wire 4 ) C [3:0] $end
|
||||
$var reg 2 * A [1:0] $end
|
||||
$var reg 2 + B [1:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 2 , A [1:0] $end
|
||||
$var wire 2 - B [1:0] $end
|
||||
$var wire 1 . c1 $end
|
||||
$var wire 1 / c2 $end
|
||||
$var wire 1 0 c5 $end
|
||||
$var wire 1 1 c4 $end
|
||||
$var wire 4 2 C [3:0] $end
|
||||
$scope module h0 $end
|
||||
$var wire 1 . A $end
|
||||
$var wire 1 / B $end
|
||||
$var wire 1 1 C $end
|
||||
$var wire 1 3 S $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 0 A $end
|
||||
$var wire 1 1 B $end
|
||||
$var wire 1 4 C $end
|
||||
$var wire 1 5 S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
05
|
||||
04
|
||||
03
|
||||
b0 2
|
||||
01
|
||||
00
|
||||
0/
|
||||
0.
|
||||
b11 -
|
||||
b0 ,
|
||||
b11 +
|
||||
b0 *
|
||||
b0 )
|
||||
x(
|
||||
x'
|
||||
x&
|
||||
x%
|
||||
z$
|
||||
x#
|
||||
z"
|
||||
z!
|
||||
$end
|
||||
#10
|
||||
b10 )
|
||||
b10 2
|
||||
13
|
||||
1/
|
||||
b10 +
|
||||
b10 -
|
||||
b1 *
|
||||
b1 ,
|
||||
#20
|
||||
1.
|
||||
0/
|
||||
b1 +
|
||||
b1 -
|
||||
b10 *
|
||||
b10 ,
|
||||
#30
|
||||
b0 )
|
||||
b0 2
|
||||
03
|
||||
0.
|
||||
b0 +
|
||||
b0 -
|
||||
b11 *
|
||||
b11 ,
|
||||
#40
|
||||
b0 *
|
||||
b0 ,
|
||||
#50
|
||||
b1 )
|
||||
b1 2
|
||||
b1 +
|
||||
b1 -
|
||||
b1 *
|
||||
b1 ,
|
||||
#60
|
||||
15
|
||||
10
|
||||
b1000 )
|
||||
b1000 2
|
||||
b10 +
|
||||
b10 -
|
||||
b10 *
|
||||
b10 ,
|
||||
#70
|
||||
05
|
||||
14
|
||||
11
|
||||
1.
|
||||
1/
|
||||
b101 )
|
||||
b101 2
|
||||
b11 +
|
||||
b11 -
|
||||
b11 *
|
||||
b11 ,
|
||||
#80
|
||||
140
labs/lab3/src/Adder3Bit
Normal file
140
labs/lab3/src/Adder3Bit
Normal file
@ -0,0 +1,140 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001e07a11e640 .scope module, "tbAdder3Bit" "tbAdder3Bit" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001e07a09f780_0 .var "r1", 2 0;
|
||||
v000001e07a09f5a0_0 .var "r2", 2 0;
|
||||
v000001e07a0a0d60_0 .net "w1", 2 0, L_000001e07a0a0ea0; 1 drivers
|
||||
v000001e07a0a0360_0 .net "w2", 2 0, L_000001e07a0a05e0; 1 drivers
|
||||
S_000001e07a11e7d0 .scope module, "uut" "Adder3Bit" 2 6, 3 1 0, S_000001e07a11e640;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 3 "num1";
|
||||
.port_info 1 /INPUT 3 "num2";
|
||||
.port_info 2 /OUTPUT 3 "Carry";
|
||||
.port_info 3 /OUTPUT 3 "sum";
|
||||
L_000001e07a118f90 .functor XOR 1, L_000001e07a09fdc0, L_000001e07a09f000, C4<0>, C4<0>;
|
||||
L_000001e07a1190e0 .functor AND 1, L_000001e07a0a0400, L_000001e07a0a0220, C4<1>, C4<1>;
|
||||
L_000001e07a119000 .functor XOR 1, L_000001e07a09fbe0, L_000001e07a0a0e00, C4<0>, C4<0>;
|
||||
L_000001e07a1191c0 .functor XOR 1, L_000001e07a119000, L_000001e07a09f8c0, C4<0>, C4<0>;
|
||||
L_000001e07a119310 .functor AND 1, L_000001e07a119000, L_000001e07a09f460, C4<1>, C4<1>;
|
||||
L_000001e07a119070 .functor AND 1, L_000001e07a09fa00, L_000001e07a0a09a0, C4<1>, C4<1>;
|
||||
L_000001e07a0a2d40 .functor OR 1, L_000001e07a119310, L_000001e07a119070, C4<0>, C4<0>;
|
||||
L_000001e07a0a25d0 .functor XOR 1, L_000001e07a09fc80, L_000001e07a0a0b80, C4<0>, C4<0>;
|
||||
L_000001e07a0a2bf0 .functor XOR 1, L_000001e07a0a25d0, L_000001e07a09faa0, C4<0>, C4<0>;
|
||||
L_000001e07a0a24f0 .functor AND 1, L_000001e07a0a25d0, L_000001e07a09f500, C4<1>, C4<1>;
|
||||
L_000001e07a0a2170 .functor AND 1, L_000001e07a09f280, L_000001e07a0a0540, C4<1>, C4<1>;
|
||||
L_000001e07a0a2640 .functor OR 1, L_000001e07a0a24f0, L_000001e07a0a2170, C4<0>, C4<0>;
|
||||
v000001e07a036150_0 .net "Carry", 2 0, L_000001e07a0a05e0; alias, 1 drivers
|
||||
v000001e07a035750_0 .net *"_ivl_1", 0 0, L_000001e07a118f90; 1 drivers
|
||||
v000001e07a0357f0_0 .net *"_ivl_11", 0 0, L_000001e07a0a0400; 1 drivers
|
||||
v000001e07a035d90_0 .net *"_ivl_13", 0 0, L_000001e07a0a0220; 1 drivers
|
||||
v000001e07a036470_0 .net *"_ivl_17", 0 0, L_000001e07a09fbe0; 1 drivers
|
||||
v000001e07a035ed0_0 .net *"_ivl_19", 0 0, L_000001e07a0a0e00; 1 drivers
|
||||
v000001e07a036510_0 .net *"_ivl_21", 0 0, L_000001e07a1191c0; 1 drivers
|
||||
v000001e07a036010_0 .net *"_ivl_25", 0 0, L_000001e07a09f8c0; 1 drivers
|
||||
v000001e07a035890_0 .net *"_ivl_30", 0 0, L_000001e07a09f460; 1 drivers
|
||||
v000001e07a0365b0_0 .net *"_ivl_34", 0 0, L_000001e07a09fa00; 1 drivers
|
||||
v000001e07a035930_0 .net *"_ivl_36", 0 0, L_000001e07a0a09a0; 1 drivers
|
||||
v000001e07a0a04a0_0 .net *"_ivl_38", 0 0, L_000001e07a0a2d40; 1 drivers
|
||||
v000001e07a0a0cc0_0 .net *"_ivl_4", 0 0, L_000001e07a09fdc0; 1 drivers
|
||||
v000001e07a09f1e0_0 .net *"_ivl_45", 0 0, L_000001e07a09fc80; 1 drivers
|
||||
v000001e07a09f140_0 .net *"_ivl_47", 0 0, L_000001e07a0a0b80; 1 drivers
|
||||
v000001e07a0a0a40_0 .net *"_ivl_49", 0 0, L_000001e07a0a2bf0; 1 drivers
|
||||
v000001e07a09f320_0 .net *"_ivl_54", 0 0, L_000001e07a09faa0; 1 drivers
|
||||
v000001e07a09fe60_0 .net *"_ivl_59", 0 0, L_000001e07a09f500; 1 drivers
|
||||
v000001e07a09f960_0 .net *"_ivl_6", 0 0, L_000001e07a09f000; 1 drivers
|
||||
v000001e07a09f820_0 .net *"_ivl_63", 0 0, L_000001e07a09f280; 1 drivers
|
||||
v000001e07a09f6e0_0 .net *"_ivl_65", 0 0, L_000001e07a0a0540; 1 drivers
|
||||
v000001e07a0a0040_0 .net *"_ivl_67", 0 0, L_000001e07a0a2640; 1 drivers
|
||||
v000001e07a09f0a0_0 .net *"_ivl_8", 0 0, L_000001e07a1190e0; 1 drivers
|
||||
v000001e07a09f640_0 .net "num1", 2 0, v000001e07a09f780_0; 1 drivers
|
||||
v000001e07a09f3c0 .array "num12", 0 1;
|
||||
v000001e07a09f3c0_0 .net v000001e07a09f3c0 0, 0 0, L_000001e07a119000; 1 drivers
|
||||
v000001e07a09f3c0_1 .net v000001e07a09f3c0 1, 0 0, L_000001e07a0a25d0; 1 drivers
|
||||
v000001e07a09ff00 .array "num12Carry", 0 1;
|
||||
v000001e07a09ff00_0 .net v000001e07a09ff00 0, 0 0, L_000001e07a119310; 1 drivers
|
||||
v000001e07a09ff00_1 .net v000001e07a09ff00 1, 0 0, L_000001e07a0a24f0; 1 drivers
|
||||
v000001e07a0a0900 .array "num1a2", 0 1;
|
||||
v000001e07a0a0900_0 .net v000001e07a0a0900 0, 0 0, L_000001e07a119070; 1 drivers
|
||||
v000001e07a0a0900_1 .net v000001e07a0a0900 1, 0 0, L_000001e07a0a2170; 1 drivers
|
||||
v000001e07a09fb40_0 .net "num2", 2 0, v000001e07a09f5a0_0; 1 drivers
|
||||
v000001e07a09fd20_0 .net "sum", 2 0, L_000001e07a0a0ea0; alias, 1 drivers
|
||||
L_000001e07a09fdc0 .part v000001e07a09f780_0, 0, 1;
|
||||
L_000001e07a09f000 .part v000001e07a09f5a0_0, 0, 1;
|
||||
L_000001e07a0a0400 .part v000001e07a09f780_0, 0, 1;
|
||||
L_000001e07a0a0220 .part v000001e07a09f5a0_0, 0, 1;
|
||||
L_000001e07a09fbe0 .part v000001e07a09f780_0, 1, 1;
|
||||
L_000001e07a0a0e00 .part v000001e07a09f5a0_0, 1, 1;
|
||||
L_000001e07a09f8c0 .part L_000001e07a0a05e0, 0, 1;
|
||||
L_000001e07a09f460 .part L_000001e07a0a05e0, 0, 1;
|
||||
L_000001e07a09fa00 .part v000001e07a09f780_0, 1, 1;
|
||||
L_000001e07a0a09a0 .part v000001e07a09f5a0_0, 1, 1;
|
||||
L_000001e07a09fc80 .part v000001e07a09f780_0, 2, 1;
|
||||
L_000001e07a0a0b80 .part v000001e07a09f5a0_0, 2, 1;
|
||||
L_000001e07a0a0ea0 .concat8 [ 1 1 1 0], L_000001e07a118f90, L_000001e07a1191c0, L_000001e07a0a2bf0;
|
||||
L_000001e07a09faa0 .part L_000001e07a0a05e0, 1, 1;
|
||||
L_000001e07a09f500 .part L_000001e07a0a05e0, 1, 1;
|
||||
L_000001e07a09f280 .part v000001e07a09f780_0, 2, 1;
|
||||
L_000001e07a0a0540 .part v000001e07a09f5a0_0, 2, 1;
|
||||
L_000001e07a0a05e0 .concat8 [ 1 1 1 0], L_000001e07a1190e0, L_000001e07a0a2d40, L_000001e07a0a2640;
|
||||
.scope S_000001e07a11e640;
|
||||
T_0 ;
|
||||
%vpi_call 2 14 "$dumpfile", "Admp.vcd" {0 0 0};
|
||||
%vpi_call 2 15 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 24 "$display", v000001e07a0a0d60_0 {0 0 0};
|
||||
%vpi_call 2 25 "$display", v000001e07a0a0360_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\tbAdder3Bit.v";
|
||||
".\Adder3Bit.v";
|
||||
15
labs/lab3/src/Adder3Bit.v
Normal file
15
labs/lab3/src/Adder3Bit.v
Normal file
@ -0,0 +1,15 @@
|
||||
module Adder3Bit (
|
||||
input [2:0] A,
|
||||
input [2:0] B,
|
||||
output [3:0] C
|
||||
);
|
||||
|
||||
wire c1, c2;
|
||||
halfAdder a0(A[0], B[0], C[0], c1);
|
||||
|
||||
fullAdder a1(A[1], B[1], c1, C[1], c2);
|
||||
fullAdder a2(A[2], B[2], c2, C[2], C[3]);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
100
labs/lab3/src/Admp.vcd
Normal file
100
labs/lab3/src/Admp.vcd
Normal file
@ -0,0 +1,100 @@
|
||||
$date
|
||||
Sat Apr 13 14:50:50 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tbAdder3Bit $end
|
||||
$var wire 3 ! w2 [2:0] $end
|
||||
$var wire 3 " w1 [2:0] $end
|
||||
$var reg 3 # r1 [2:0] $end
|
||||
$var reg 3 $ r2 [2:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 3 % num1 [2:0] $end
|
||||
$var wire 3 & num2 [2:0] $end
|
||||
$var wire 3 ' sum [2:0] $end
|
||||
$var wire 3 ( Carry [2:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
b0 (
|
||||
b0 '
|
||||
b0 &
|
||||
b0 %
|
||||
b0 $
|
||||
b0 #
|
||||
b0 "
|
||||
b0 !
|
||||
$end
|
||||
#10
|
||||
b10 "
|
||||
b10 '
|
||||
b1 !
|
||||
b1 (
|
||||
b1 $
|
||||
b1 &
|
||||
b1 #
|
||||
b1 %
|
||||
#20
|
||||
b100 "
|
||||
b100 '
|
||||
b10 !
|
||||
b10 (
|
||||
b10 $
|
||||
b10 &
|
||||
b10 #
|
||||
b10 %
|
||||
#30
|
||||
b0 "
|
||||
b0 '
|
||||
b100 !
|
||||
b100 (
|
||||
b100 $
|
||||
b100 &
|
||||
b100 #
|
||||
b100 %
|
||||
#40
|
||||
b110 "
|
||||
b110 '
|
||||
b11 !
|
||||
b11 (
|
||||
b11 $
|
||||
b11 &
|
||||
b11 #
|
||||
b11 %
|
||||
#50
|
||||
b10 "
|
||||
b10 '
|
||||
b101 !
|
||||
b101 (
|
||||
b101 $
|
||||
b101 &
|
||||
b101 #
|
||||
b101 %
|
||||
#60
|
||||
b100 "
|
||||
b100 '
|
||||
b110 !
|
||||
b110 (
|
||||
b110 $
|
||||
b110 &
|
||||
b110 #
|
||||
b110 %
|
||||
#70
|
||||
b110 "
|
||||
b110 '
|
||||
b111 !
|
||||
b111 (
|
||||
b111 $
|
||||
b111 &
|
||||
b111 #
|
||||
b111 %
|
||||
#80
|
||||
234
labs/lab3/src/dmp.vcd
Normal file
234
labs/lab3/src/dmp.vcd
Normal file
@ -0,0 +1,234 @@
|
||||
$date
|
||||
Fri May 03 11:28:11 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 4 ! C [3:0] $end
|
||||
$var reg 3 " A [2:0] $end
|
||||
$var reg 3 # B [2:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 3 $ A [2:0] $end
|
||||
$var wire 3 % B [2:0] $end
|
||||
$var wire 1 & c2 $end
|
||||
$var wire 1 ' c1 $end
|
||||
$var wire 4 ( C [3:0] $end
|
||||
$scope module a0 $end
|
||||
$var wire 1 ) A $end
|
||||
$var wire 1 * B $end
|
||||
$var wire 1 ' C $end
|
||||
$var wire 1 + S $end
|
||||
$upscope $end
|
||||
$scope module a1 $end
|
||||
$var wire 1 , A $end
|
||||
$var wire 1 - B $end
|
||||
$var wire 1 & C $end
|
||||
$var wire 1 ' Z $end
|
||||
$var wire 1 . W2 $end
|
||||
$var wire 1 / W1 $end
|
||||
$var wire 1 0 W0 $end
|
||||
$var wire 1 1 S $end
|
||||
$scope module h0 $end
|
||||
$var wire 1 , A $end
|
||||
$var wire 1 - B $end
|
||||
$var wire 1 / C $end
|
||||
$var wire 1 0 S $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 0 A $end
|
||||
$var wire 1 ' B $end
|
||||
$var wire 1 . C $end
|
||||
$var wire 1 1 S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module a2 $end
|
||||
$var wire 1 2 A $end
|
||||
$var wire 1 3 B $end
|
||||
$var wire 1 4 C $end
|
||||
$var wire 1 & Z $end
|
||||
$var wire 1 5 W2 $end
|
||||
$var wire 1 6 W1 $end
|
||||
$var wire 1 7 W0 $end
|
||||
$var wire 1 8 S $end
|
||||
$scope module h0 $end
|
||||
$var wire 1 2 A $end
|
||||
$var wire 1 3 B $end
|
||||
$var wire 1 6 C $end
|
||||
$var wire 1 7 S $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 7 A $end
|
||||
$var wire 1 & B $end
|
||||
$var wire 1 5 C $end
|
||||
$var wire 1 8 S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
18
|
||||
17
|
||||
06
|
||||
05
|
||||
04
|
||||
13
|
||||
02
|
||||
11
|
||||
10
|
||||
0/
|
||||
0.
|
||||
1-
|
||||
0,
|
||||
1+
|
||||
1*
|
||||
0)
|
||||
b111 (
|
||||
0'
|
||||
0&
|
||||
b111 %
|
||||
b0 $
|
||||
b111 #
|
||||
b0 "
|
||||
b111 !
|
||||
$end
|
||||
#10
|
||||
0*
|
||||
1)
|
||||
b110 #
|
||||
b110 %
|
||||
b1 "
|
||||
b1 $
|
||||
#20
|
||||
1*
|
||||
0-
|
||||
0)
|
||||
1,
|
||||
b101 #
|
||||
b101 %
|
||||
b10 "
|
||||
b10 $
|
||||
#30
|
||||
0*
|
||||
1)
|
||||
b100 #
|
||||
b100 %
|
||||
b11 "
|
||||
b11 $
|
||||
#40
|
||||
1*
|
||||
1-
|
||||
03
|
||||
0)
|
||||
0,
|
||||
12
|
||||
b11 #
|
||||
b11 %
|
||||
b100 "
|
||||
b100 $
|
||||
#50
|
||||
0*
|
||||
1)
|
||||
b10 #
|
||||
b10 %
|
||||
b101 "
|
||||
b101 $
|
||||
#60
|
||||
1*
|
||||
0-
|
||||
0)
|
||||
1,
|
||||
b1 #
|
||||
b1 %
|
||||
b110 "
|
||||
b110 $
|
||||
#70
|
||||
0*
|
||||
1)
|
||||
b0 #
|
||||
b0 %
|
||||
b111 "
|
||||
b111 $
|
||||
#80
|
||||
01
|
||||
08
|
||||
b0 !
|
||||
b0 (
|
||||
0+
|
||||
00
|
||||
07
|
||||
0)
|
||||
0,
|
||||
02
|
||||
b0 "
|
||||
b0 $
|
||||
#90
|
||||
b1 !
|
||||
b1 (
|
||||
1+
|
||||
1)
|
||||
b1 "
|
||||
b1 $
|
||||
#100
|
||||
11
|
||||
b10 !
|
||||
b10 (
|
||||
0+
|
||||
10
|
||||
0)
|
||||
1,
|
||||
b10 "
|
||||
b10 $
|
||||
#110
|
||||
b11 !
|
||||
b11 (
|
||||
1+
|
||||
1)
|
||||
b11 "
|
||||
b11 $
|
||||
#120
|
||||
01
|
||||
18
|
||||
b100 !
|
||||
b100 (
|
||||
0+
|
||||
00
|
||||
17
|
||||
0)
|
||||
0,
|
||||
12
|
||||
b100 "
|
||||
b100 $
|
||||
#130
|
||||
b101 !
|
||||
b101 (
|
||||
1+
|
||||
1)
|
||||
b101 "
|
||||
b101 $
|
||||
#140
|
||||
11
|
||||
b110 !
|
||||
b110 (
|
||||
0+
|
||||
10
|
||||
0)
|
||||
1,
|
||||
b110 "
|
||||
b110 $
|
||||
#150
|
||||
b111 !
|
||||
b111 (
|
||||
1+
|
||||
1)
|
||||
b111 "
|
||||
b111 $
|
||||
#160
|
||||
12
labs/lab3/src/fullAdder.v
Normal file
12
labs/lab3/src/fullAdder.v
Normal file
@ -0,0 +1,12 @@
|
||||
module fullAdder(
|
||||
input A, B, Z,
|
||||
output S, C
|
||||
);
|
||||
wire W0, W1, W2;
|
||||
|
||||
halfAdder h0(A, B, W0, W1);
|
||||
halfAdder h1(W0, Z, S, W2);
|
||||
|
||||
or(C, W1, W2);
|
||||
|
||||
endmodule
|
||||
9
labs/lab3/src/halfAdder.v
Normal file
9
labs/lab3/src/halfAdder.v
Normal file
@ -0,0 +1,9 @@
|
||||
module halfAdder(
|
||||
input A, B,
|
||||
output S, C
|
||||
);
|
||||
|
||||
xor(S, A, B);
|
||||
and(C, A, B);
|
||||
|
||||
endmodule
|
||||
23
labs/lab3/src/mtb.v
Normal file
23
labs/lab3/src/mtb.v
Normal file
@ -0,0 +1,23 @@
|
||||
module mtb();
|
||||
|
||||
reg[1:0] A, B;
|
||||
wire [3:0] C;
|
||||
mult2bit uut(A,B,C);
|
||||
|
||||
initial begin
|
||||
$dumpfile("3dmp.vcd");
|
||||
$dumpvars;
|
||||
|
||||
A = 2'd0; B = 2'd3; #10;
|
||||
A = 2'd1; B = 2'd2; #10;
|
||||
A = 2'd2; B = 2'd1; #10;
|
||||
A = 2'd3; B = 2'd0; #10;
|
||||
|
||||
A = 2'd0; B = 2'd0; #10;
|
||||
A = 2'd1; B = 2'd1; #10;
|
||||
A = 2'd2; B = 2'd2; #10;
|
||||
A = 2'd3; B = 2'd3; #10;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
169
labs/lab3/src/mult2
Normal file
169
labs/lab3/src/mult2
Normal file
@ -0,0 +1,169 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_0000025ecd40d010 .scope module, "fullAdder" "fullAdder" 2 1;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Z";
|
||||
.port_info 3 /OUTPUT 1 "S";
|
||||
.port_info 4 /OUTPUT 1 "C";
|
||||
L_0000025ecd257f60 .functor OR 1, L_0000025ecd258660, L_0000025ecd2585f0, C4<0>, C4<0>;
|
||||
o0000025ecd26dfb8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
v0000025ecd25a670_0 .net "A", 0 0, o0000025ecd26dfb8; 0 drivers
|
||||
o0000025ecd26dfe8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
v0000025ecd25ae90_0 .net "B", 0 0, o0000025ecd26dfe8; 0 drivers
|
||||
v0000025ecd25a710_0 .net "C", 0 0, L_0000025ecd257f60; 1 drivers
|
||||
v0000025ecd25a8f0_0 .net "S", 0 0, L_0000025ecd258580; 1 drivers
|
||||
v0000025ecd25afd0_0 .net "W0", 0 0, L_0000025ecd2584a0; 1 drivers
|
||||
v0000025ecd25a990_0 .net "W1", 0 0, L_0000025ecd258660; 1 drivers
|
||||
v0000025ecd25aa30_0 .net "W2", 0 0, L_0000025ecd2585f0; 1 drivers
|
||||
o0000025ecd26e138 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
v0000025ecd25b070_0 .net "Z", 0 0, o0000025ecd26e138; 0 drivers
|
||||
S_0000025ecd40e9d0 .scope module, "h0" "halfAdder" 2 7, 3 1 0, S_0000025ecd40d010;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0000025ecd2584a0 .functor XOR 1, o0000025ecd26dfb8, o0000025ecd26dfe8, C4<0>, C4<0>;
|
||||
L_0000025ecd258660 .functor AND 1, o0000025ecd26dfb8, o0000025ecd26dfe8, C4<1>, C4<1>;
|
||||
v0000025ecd25a530_0 .net "A", 0 0, o0000025ecd26dfb8; alias, 0 drivers
|
||||
v0000025ecd25adf0_0 .net "B", 0 0, o0000025ecd26dfe8; alias, 0 drivers
|
||||
v0000025ecd25a5d0_0 .net "C", 0 0, L_0000025ecd258660; alias, 1 drivers
|
||||
v0000025ecd25b2f0_0 .net "S", 0 0, L_0000025ecd2584a0; alias, 1 drivers
|
||||
S_0000025ecd40eb60 .scope module, "h1" "halfAdder" 2 8, 3 1 0, S_0000025ecd40d010;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0000025ecd258580 .functor XOR 1, L_0000025ecd2584a0, o0000025ecd26e138, C4<0>, C4<0>;
|
||||
L_0000025ecd2585f0 .functor AND 1, L_0000025ecd2584a0, o0000025ecd26e138, C4<1>, C4<1>;
|
||||
v0000025ecd25b110_0 .net "A", 0 0, L_0000025ecd2584a0; alias, 1 drivers
|
||||
v0000025ecd25a850_0 .net "B", 0 0, o0000025ecd26e138; alias, 0 drivers
|
||||
v0000025ecd25b1b0_0 .net "C", 0 0, L_0000025ecd2585f0; alias, 1 drivers
|
||||
v0000025ecd25a3f0_0 .net "S", 0 0, L_0000025ecd258580; alias, 1 drivers
|
||||
S_0000025ecd40d1a0 .scope module, "mtb" "mtb" 4 1;
|
||||
.timescale 0 0;
|
||||
v0000025ecd2c1fb0_0 .var "A", 1 0;
|
||||
v0000025ecd2c1bf0_0 .var "B", 1 0;
|
||||
v0000025ecd2c1f10_0 .net "C", 3 0, L_0000025ecd2c0f70; 1 drivers
|
||||
S_0000025ecd26aae0 .scope module, "uut" "mult2bit" 4 5, 5 1 0, S_0000025ecd40d1a0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 2 "A";
|
||||
.port_info 1 /INPUT 2 "B";
|
||||
.port_info 2 /OUTPUT 4 "C";
|
||||
L_0000025ecd257fd0 .functor AND 1, L_0000025ecd2c1dd0, L_0000025ecd2c0ed0, C4<1>, C4<1>;
|
||||
L_0000025ecd2c2a60 .functor AND 1, L_0000025ecd2c2230, L_0000025ecd2c0890, C4<1>, C4<1>;
|
||||
L_0000025ecd2c2de0 .functor AND 1, L_0000025ecd2c0b10, L_0000025ecd2c22d0, C4<1>, C4<1>;
|
||||
L_0000025ecd2c28a0 .functor AND 1, L_0000025ecd2c2410, L_0000025ecd2c24b0, C4<1>, C4<1>;
|
||||
v0000025ecd2c15b0_0 .net "A", 1 0, v0000025ecd2c1fb0_0; 1 drivers
|
||||
v0000025ecd2c1d30_0 .net "B", 1 0, v0000025ecd2c1bf0_0; 1 drivers
|
||||
v0000025ecd2c0bb0_0 .net "C", 3 0, L_0000025ecd2c0f70; alias, 1 drivers
|
||||
v0000025ecd2c1e70_0 .net *"_ivl_1", 0 0, L_0000025ecd2c1dd0; 1 drivers
|
||||
v0000025ecd2c1830_0 .net *"_ivl_11", 0 0, L_0000025ecd2c22d0; 1 drivers
|
||||
v0000025ecd2c0c50_0 .net *"_ivl_12", 0 0, L_0000025ecd2c28a0; 1 drivers
|
||||
v0000025ecd2c2370_0 .net *"_ivl_15", 0 0, L_0000025ecd2c2410; 1 drivers
|
||||
v0000025ecd2c18d0_0 .net *"_ivl_17", 0 0, L_0000025ecd2c24b0; 1 drivers
|
||||
v0000025ecd2c2690_0 .net *"_ivl_3", 0 0, L_0000025ecd2c0ed0; 1 drivers
|
||||
v0000025ecd2c0a70_0 .net *"_ivl_5", 0 0, L_0000025ecd2c2230; 1 drivers
|
||||
v0000025ecd2c0cf0_0 .net *"_ivl_7", 0 0, L_0000025ecd2c0890; 1 drivers
|
||||
v0000025ecd2c1c90_0 .net *"_ivl_9", 0 0, L_0000025ecd2c0b10; 1 drivers
|
||||
v0000025ecd2c1470_0 .net "c1", 0 0, L_0000025ecd257fd0; 1 drivers
|
||||
v0000025ecd2c2190_0 .net "c2", 0 0, L_0000025ecd2c2a60; 1 drivers
|
||||
v0000025ecd2c1650_0 .net "c4", 0 0, L_0000025ecd2c2f30; 1 drivers
|
||||
v0000025ecd2c0d90_0 .net "c5", 0 0, L_0000025ecd2c2de0; 1 drivers
|
||||
L_0000025ecd2c1dd0 .part v0000025ecd2c1fb0_0, 1, 1;
|
||||
L_0000025ecd2c0ed0 .part v0000025ecd2c1bf0_0, 0, 1;
|
||||
L_0000025ecd2c2230 .part v0000025ecd2c1fb0_0, 0, 1;
|
||||
L_0000025ecd2c0890 .part v0000025ecd2c1bf0_0, 1, 1;
|
||||
L_0000025ecd2c0b10 .part v0000025ecd2c1fb0_0, 1, 1;
|
||||
L_0000025ecd2c22d0 .part v0000025ecd2c1bf0_0, 1, 1;
|
||||
L_0000025ecd2c2410 .part v0000025ecd2c1fb0_0, 0, 1;
|
||||
L_0000025ecd2c24b0 .part v0000025ecd2c1bf0_0, 0, 1;
|
||||
L_0000025ecd2c0f70 .concat8 [ 1 1 1 1], L_0000025ecd2c28a0, L_0000025ecd2c35c0, L_0000025ecd2c2fa0, L_0000025ecd2c32b0;
|
||||
S_0000025ecd26ac70 .scope module, "h0" "halfAdder" 5 14, 3 1 0, S_0000025ecd26aae0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0000025ecd2c35c0 .functor XOR 1, L_0000025ecd257fd0, L_0000025ecd2c2a60, C4<0>, C4<0>;
|
||||
L_0000025ecd2c2f30 .functor AND 1, L_0000025ecd257fd0, L_0000025ecd2c2a60, C4<1>, C4<1>;
|
||||
v0000025ecd25ab70_0 .net "A", 0 0, L_0000025ecd257fd0; alias, 1 drivers
|
||||
v0000025ecd25acb0_0 .net "B", 0 0, L_0000025ecd2c2a60; alias, 1 drivers
|
||||
v0000025ecd25ad50_0 .net "C", 0 0, L_0000025ecd2c2f30; alias, 1 drivers
|
||||
v0000025ecd25af30_0 .net "S", 0 0, L_0000025ecd2c35c0; 1 drivers
|
||||
S_0000025ecd232990 .scope module, "h1" "halfAdder" 5 15, 3 1 0, S_0000025ecd26aae0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0000025ecd2c32b0 .functor XOR 1, L_0000025ecd2c2de0, L_0000025ecd2c2f30, C4<0>, C4<0>;
|
||||
L_0000025ecd2c2fa0 .functor AND 1, L_0000025ecd2c2de0, L_0000025ecd2c2f30, C4<1>, C4<1>;
|
||||
v0000025ecd2c25f0_0 .net "A", 0 0, L_0000025ecd2c2de0; alias, 1 drivers
|
||||
v0000025ecd2c1330_0 .net "B", 0 0, L_0000025ecd2c2f30; alias, 1 drivers
|
||||
v0000025ecd2c09d0_0 .net "C", 0 0, L_0000025ecd2c2fa0; 1 drivers
|
||||
v0000025ecd2c1b50_0 .net "S", 0 0, L_0000025ecd2c32b0; 1 drivers
|
||||
.scope S_0000025ecd40d1a0;
|
||||
T_0 ;
|
||||
%vpi_call 4 8 "$dumpfile", "3dmp.vcd" {0 0 0};
|
||||
%vpi_call 4 9 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 6;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\fullAdder.v";
|
||||
".\halfAdder.v";
|
||||
".\mtb.v";
|
||||
".\mult2bit.v";
|
||||
17
labs/lab3/src/mult2bit.v
Normal file
17
labs/lab3/src/mult2bit.v
Normal file
@ -0,0 +1,17 @@
|
||||
module mult2bit (
|
||||
input [1:0] A,
|
||||
input [1:0] B,
|
||||
output [3:0] C
|
||||
);
|
||||
|
||||
wire c1, c2, c4, c5;
|
||||
|
||||
and a0(c1, A[1], B[0]);
|
||||
and a1(c2, A[0], B[1]);
|
||||
and a2(c5, A[1], B[1]);
|
||||
and a3(C[0], A[0], B[0]);
|
||||
|
||||
halfAdder h0(c1, c2, C[1], c4);
|
||||
halfAdder h1(c5, c4, C[3], C[2]);
|
||||
|
||||
endmodule
|
||||
31
labs/lab3/src/tb.v
Normal file
31
labs/lab3/src/tb.v
Normal file
@ -0,0 +1,31 @@
|
||||
module tb();
|
||||
|
||||
reg [2:0] A, B;
|
||||
wire [3:0] C;
|
||||
Adder3Bit uut(A, B, C);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
|
||||
A = 3'd0; B = 3'd7; #10;
|
||||
A = 3'd1; B = 3'd6; #10;
|
||||
A = 3'd2; B = 3'd5; #10;
|
||||
A = 3'd3; B = 3'd4; #10;
|
||||
A = 3'd4; B = 3'd3; #10;
|
||||
A = 3'd5; B = 3'd2; #10;
|
||||
A = 3'd6; B = 3'd1; #10;
|
||||
A = 3'd7; B = 3'd0; #10;
|
||||
|
||||
A = 3'd0; B = 3'd0; #10;
|
||||
A = 3'd1; B = 3'd0; #10;
|
||||
A = 3'd2; B = 3'd0; #10;
|
||||
A = 3'd3; B = 3'd0; #10;
|
||||
A = 3'd4; B = 3'd0; #10;
|
||||
A = 3'd5; B = 3'd0; #10;
|
||||
A = 3'd6; B = 3'd0; #10;
|
||||
A = 3'd7; B = 3'd0; #10;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user