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verilog

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This commit is contained in:
k0rrluna
2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
136 changed files with 11599 additions and 0 deletions
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77
labs/lab2_prep/src/dmp.vcd Normal file
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$date
Thu Apr 11 06:20:47 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb $end
$var wire 1 ! w1 $end
$var reg 1 " r1 $end
$var reg 1 # r2 $end
$var reg 1 $ r3 $end
$var reg 1 % r4 $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 & AD $end
$var wire 1 ' An $end
$var wire 1 ( AnBC $end
$var wire 1 # B $end
$var wire 1 ) Bn $end
$var wire 1 $ C $end
$var wire 1 * Cn $end
$var wire 1 + CnD $end
$var wire 1 % D $end
$var wire 1 ! F $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
0+
1*
1)
0(
1'
0&
0%
0$
0#
0"
1!
$end
#50
1+
1%
#100
0+
0*
0%
1$
#150
1%
#200
0!
1*
0)
0%
0$
1#
#250
1!
1+
1%
#300
0+
1(
0*
0%
1$
#350
1%
#400

126
labs/lab2_prep/src/lab Normal file
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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001e2946aad20 .scope module, "tb" "tb" 2 1;
.timescale 0 0;
v000001e29475e7f0_0 .var "r1", 0 0;
v000001e29475e6b0_0 .var "r2", 0 0;
v000001e29475ec50_0 .var "r3", 0 0;
v000001e29475e430_0 .var "r4", 0 0;
v000001e29475ecf0_0 .net "w1", 0 0, L_000001e29475f0f0; 1 drivers
S_000001e294717fc0 .scope module, "uut" "lab2" 2 6, 3 1 0, S_000001e2946aad20;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "F";
L_000001e2947183d0 .functor NOT 1, v000001e29475e7f0_0, C4<0>, C4<0>, C4<0>;
L_000001e2946e2bc0 .functor AND 1, L_000001e2947183d0, v000001e29475e6b0_0, v000001e29475ec50_0, C4<1>;
L_000001e2946e2d20 .functor NOT 1, v000001e29475e6b0_0, C4<0>, C4<0>, C4<0>;
L_000001e29475f390 .functor AND 1, v000001e29475e7f0_0, v000001e29475e430_0, C4<1>, C4<1>;
L_000001e29475f4e0 .functor NOT 1, v000001e29475ec50_0, C4<0>, C4<0>, C4<0>;
L_000001e29475f780 .functor AND 1, L_000001e29475f4e0, v000001e29475e430_0, C4<1>, C4<1>;
L_000001e29475f0f0 .functor OR 1, L_000001e2946e2bc0, L_000001e2946e2d20, L_000001e29475f390, L_000001e29475f780;
v000001e2946e2a40_0 .net "A", 0 0, v000001e29475e7f0_0; 1 drivers
v000001e2946e28d0_0 .net "AD", 0 0, L_000001e29475f390; 1 drivers
v000001e2946a9e10_0 .net "An", 0 0, L_000001e2947183d0; 1 drivers
v000001e2946aaeb0_0 .net "AnBC", 0 0, L_000001e2946e2bc0; 1 drivers
v000001e294718150_0 .net "B", 0 0, v000001e29475e6b0_0; 1 drivers
v000001e2947181f0_0 .net "Bn", 0 0, L_000001e2946e2d20; 1 drivers
v000001e294718290_0 .net "C", 0 0, v000001e29475ec50_0; 1 drivers
v000001e294718330_0 .net "Cn", 0 0, L_000001e29475f4e0; 1 drivers
v000001e294714e50_0 .net "CnD", 0 0, L_000001e29475f780; 1 drivers
v000001e294714ef0_0 .net "D", 0 0, v000001e29475e430_0; 1 drivers
v000001e29475e390_0 .net "F", 0 0, L_000001e29475f0f0; alias, 1 drivers
.scope S_000001e2946aad20;
T_0 ;
%vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0};
%vpi_call 2 18 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%vpi_call 2 27 "$display", v000001e29475ecf0_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb.v";
"lab2.v";

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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_0000016d6fd625e0 .scope module, "lab2" "lab2" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "F";
o0000016d6fd96f98 .functor BUFZ 1, C4<z>; HiZ drive
L_0000016d6fd62f70 .functor NOT 1, o0000016d6fd96f98, C4<0>, C4<0>, C4<0>;
o0000016d6fd97058 .functor BUFZ 1, C4<z>; HiZ drive
o0000016d6fd970b8 .functor BUFZ 1, C4<z>; HiZ drive
L_0000016d6fedb7d0 .functor AND 1, L_0000016d6fd62f70, o0000016d6fd97058, o0000016d6fd970b8, C4<1>;
L_0000016d6fedb840 .functor NOT 1, o0000016d6fd97058, C4<0>, C4<0>, C4<0>;
o0000016d6fd97148 .functor BUFZ 1, C4<z>; HiZ drive
L_0000016d6fedb8b0 .functor AND 1, o0000016d6fd96f98, o0000016d6fd97148, C4<1>, C4<1>;
L_0000016d6fedb920 .functor NOT 1, o0000016d6fd970b8, C4<0>, C4<0>, C4<0>;
L_0000016d6fedb990 .functor AND 1, L_0000016d6fedb920, o0000016d6fd97148, C4<1>, C4<1>;
L_0000016d6fedba00 .functor OR 1, L_0000016d6fedb7d0, L_0000016d6fedb840, L_0000016d6fedb8b0, L_0000016d6fedb990;
v0000016d6fd62b30_0 .net "A", 0 0, o0000016d6fd96f98; 0 drivers
v0000016d6fd62d50_0 .net "AD", 0 0, L_0000016d6fedb8b0; 1 drivers
v0000016d6fd62770_0 .net "An", 0 0, L_0000016d6fd62f70; 1 drivers
v0000016d6fd62810_0 .net "AnBC", 0 0, L_0000016d6fedb7d0; 1 drivers
v0000016d6fd628b0_0 .net "B", 0 0, o0000016d6fd97058; 0 drivers
v0000016d6fededb0_0 .net "Bn", 0 0, L_0000016d6fedb840; 1 drivers
v0000016d6fedee50_0 .net "C", 0 0, o0000016d6fd970b8; 0 drivers
v0000016d6fedeef0_0 .net "Cn", 0 0, L_0000016d6fedb920; 1 drivers
v0000016d6fedb600_0 .net "CnD", 0 0, L_0000016d6fedb990; 1 drivers
v0000016d6fedb730_0 .net "D", 0 0, o0000016d6fd97148; 0 drivers
v0000016d6fd90c30_0 .net "F", 0 0, L_0000016d6fedba00; 1 drivers
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"lab2.v";

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labs/lab2_prep/src/lab2.v Normal file
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module lab2(
input A,
input B,
input C,
input D,
output F
);
wire An, Bn, Cn;
wire AnBC, AD, CnD;
not n1 (An, A);
and (AnBC, An, B, C);
not (Bn, B);
and (AD, A, D);
not (Cn, C);
and (CnD, Cn, D);
or (F, AnBC, Bn, AD, CnD);
endmodule

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labs/lab2_prep/src/labwave Normal file
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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001e0df4625e0 .scope module, "f_lab2" "f_lab2" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "F";
o000001e0df496fd8 .functor BUFZ 1, C4<z>; HiZ drive
L_000001e0df462f70 .functor NOT 1, o000001e0df496fd8, C4<0>, C4<0>, C4<0>;
o000001e0df497098 .functor BUFZ 1, C4<z>; HiZ drive
o000001e0df4970f8 .functor BUFZ 1, C4<z>; HiZ drive
L_000001e0df64aa10 .functor AND 1, L_000001e0df462f70, o000001e0df497098, o000001e0df4970f8, C4<1>;
L_000001e0df64aa80 .functor NOT 1, o000001e0df497098, C4<0>, C4<0>, C4<0>;
o000001e0df497188 .functor BUFZ 1, C4<z>; HiZ drive
L_000001e0df64aaf0 .functor AND 1, o000001e0df496fd8, o000001e0df497188, C4<1>, C4<1>;
L_000001e0df64ab60 .functor NOT 1, o000001e0df4970f8, C4<0>, C4<0>, C4<0>;
L_000001e0df64abd0 .functor AND 1, L_000001e0df64ab60, o000001e0df497188, C4<1>, C4<1>;
L_000001e0df64ac40 .functor OR 1, L_000001e0df64aa10, L_000001e0df64aa80, L_000001e0df64aaf0, L_000001e0df64abd0;
v000001e0df462b30_0 .net "A", 0 0, o000001e0df496fd8; 0 drivers
v000001e0df462d50_0 .net "AD", 0 0, L_000001e0df64aaf0; 1 drivers
v000001e0df462770_0 .net "An", 0 0, L_000001e0df462f70; 1 drivers
v000001e0df462810_0 .net "AnBC", 0 0, L_000001e0df64aa10; 1 drivers
v000001e0df4628b0_0 .net "B", 0 0, o000001e0df497098; 0 drivers
v000001e0df64ed90_0 .net "Bn", 0 0, L_000001e0df64aa80; 1 drivers
v000001e0df64ee30_0 .net "C", 0 0, o000001e0df4970f8; 0 drivers
v000001e0df64eed0_0 .net "Cn", 0 0, L_000001e0df64ab60; 1 drivers
v000001e0df64a840_0 .net "CnD", 0 0, L_000001e0df64abd0; 1 drivers
v000001e0df64a970_0 .net "D", 0 0, o000001e0df497188; 0 drivers
v000001e0df492660_0 .net "F", 0 0, L_000001e0df64ac40; 1 drivers
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
".\f_lab2.v";

32
labs/lab2_prep/src/tb.v Normal file
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module tb();
reg r1, r2, r3, r4;
wire w1;
lab2 uut(
.A(r1),
.B(r2),
.C(r3),
.D(r4),
.F(w1)
);
// test uut(r1, r2, w1, w2, w3);
initial begin
$dumpfile("dmp.vcd");
$dumpvars;
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b0; #50;
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b1; #50;
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b0; #50;
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b1; #50;
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b0; #50;
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b1; #50;
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b0; #50;
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b1; #50;
$display(w1);
end
endmodule