kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

verilog

Browse Source
This commit is contained in:
k0rrluna
2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
136 changed files with 11599 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
labs/lab2_prep/impl/gwsynthesis/lab2_syn_resource.html Normal file
View File

@@ -0,0 +1,46 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">tb (C:/cygwin64/home/koray/verilog/lab2/src/tb.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>