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verilog

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This commit is contained in:
k0rrluna
2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
136 changed files with 11599 additions and 0 deletions
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labs/lab2/lab2.gprj Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/BitM.v" type="file.verilog" enable="1"/>
<File path="src/fullAdder.v" type="file.verilog" enable="1"/>
<File path="src/halfAdder.v" type="file.verilog" enable="1"/>
<File path="src/tb.v" type="file.verilog" enable="1"/>
</FileList>
</Project>